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SN54ALS563BW

更新时间： 2024-11-05 23:06:11
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路输出元件
页数 文件大小 规格书
5页 85K
描述
OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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中文翻译

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SN54ALS563BW 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：CERAMIC, FP-20针数：20
Reach Compliance Code：unknownECCN代码：3A001.A.2.C
HTS代码：8542.39.00.01风险等级：5.79
Is Samacsys：N其他特性：BROADSIDE VERSION OF 533
系列：ALSJESD-30 代码：R-GDFP-F20
长度：13.09 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK最大电源电流（ICC）：26 mA
传播延迟（tpd）：22 ns认证状态：Not Qualified
座面最大高度：2.54 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
宽度：6.92 mmBase Number Matches：1

SN54ALS563BW 数据手册

 浏览型号SN54ALS563BW的Datasheet PDF文件第2页浏览型号SN54ALS563BW的Datasheet PDF文件第3页浏览型号SN54ALS563BW的Datasheet PDF文件第4页浏览型号SN54ALS563BW的Datasheet PDF文件第5页 
SN54ALS563B, SN74ALS563B  
OCTAL D-TYPE TRANSPARENT LATCHES  
WITH 3-STATE OUTPUTS  
SDAS163A – DECEMBER 1982 – REVISED JANUARY 1995  
SN54ALS563B . . . J OR W PACKAGE  
SN74ALS563B . . . DW OR N PACKAGE  
(TOP VIEW)  
• 3-State Buffer-Type Outputs Drive Bus  
Lines Directly  
• Bus-Structured Pinout  
• Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs, and Ceramic Flat  
(W) Packages  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
description  
13 7Q  
12 8Q  
These 8-bit D-type transparent latches feature  
3-state outputs designed specifically for driving  
highly capacitive or relatively low-impedance  
loads. They are particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
11  
GND  
LE  
SN54ALS563B . . . FK PACKAGE  
(TOP VIEW)  
While the latch-enable (LE) input is high, the Q  
outputs follow the complements of data (D) inputs.  
When LE is taken low, the outputs are latched at  
the inverses of the levels set up at the D inputs.  
3
2
1
20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
A buffered output-enable (OE) input places the  
eight outputs in either a normal logic state (high or  
low logic levels) or a high-impedance state. In the  
high-impedance state, the outputs neither load  
nor drive the bus lines significantly. The  
high-impedance state and increased high logic  
level provide the capability to drive bus lines  
without interface or pullup components.  
9 10 11 12 13  
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
The SN54ALS563B is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ALS563B is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
H
X
X
L
L
H
L
Q
0
H
X
Z
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345

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