SN54ALS259

更新时间： 2024-11-22 23:06:11

品牌	Logo	应用领域
德州仪器 - TI		锁存器双倍数据速率
页数	文件大小	规格书
7页	120K
描述
8-BIT ADDRESSABLE LATCHES

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

SN54ALS259 数据手册

SN54ALS259, SN74ALS259

8-BIT ADDRESSABLE LATCHES

SDAS217A – DECEMBER 1982 – REVISED DECEMBER 1994

SN54ALS259 . . . J PACKAGE

SN74ALS259 . . . D OR N PACKAGE

(TOP VIEW)

• 8-Bit Parallel-Out Storage Register

Performs Serial-to-Parallel Conversion With

Storage

• Asynchronous Parallel Clear

• Active-High Decoder

• Enable/Disable Input Simplifies Expansion

• Expandable for n-Bit Applications

• Four Distinct Functional Modes

• Package Options Include Plastic

Small-Outline (D) Packages, Ceramic Chip

Carriers (FK), and Standard Plastic (N) and

Ceramic (J) 300-mil DIPs

GND

CLR

SN54ALS259 . . . FK PACKAGE

(TOP VIEW)

description

These 8-bit addressable latches are designed for

general-purpose storage applications in digital

systems. Specific uses include working registers,

serial-holding registers, and active-high decoders

or demultiplexers. They are multifunctional

devices capable of storing single-line data in eight

addressablelatchesandbeinga1-of-8decoderor

demultiplexer with active-high outputs.

1 20 19

9 10 11 12 13

Four distinct modes of operation are selectable by

controlling the clear (CLR) and enable (G) inputs

as shown in the function table. In the

addressable-latch mode, data at the data-in

terminal is written into the addressed latch. The

NC – No internal connection

addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the

memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To

eliminate the possibility of entering erroneous data in the latches, G should be held high (inactive) while the

address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the

level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address

and data inputs.

The SN54ALS259 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ALS259 is characterized for operation from 0°C to 70°C.

Function Tables

FUNCTION

OUTPUT OF

EACH

INPUTS

ADDRESSED OTHER

FUNCTION

CLR

LATCH

OUTPUT

Addressable latch

Memory

8-line demultiplexer

Clear

D = the level at the data input.

= the level of Q (i = Q, 1, . . . 7 as appropriate) before the indicated

steady-state input conditions were established.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

中文翻译

下载PDF

SN54ALS259 替代型号

型号	品牌	替代类型	描述	数据表
SN74ALS259	TI	功能相似	8-BIT ADDRESSABLE LATCHES

与SN54ALS259相关器件

型号	品牌	获取价格	描述	数据表
SN54ALS259FH	ROCHESTER	获取价格	D Latch
SN54ALS259FH	TI	获取价格	IC,LATCH,SINGLE,8-BIT,ALS-TTL,LLCC,20PIN,CERAMIC
SN54ALS259FK	TI	获取价格	8-BIT ADDRESSABLE LATCHES
SN54ALS259J	TI	获取价格	8-BIT ADDRESSABLE LATCHES
SN54ALS273	TI	获取价格	OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
SN54ALS273FH	TI	获取价格	IC,FLIP-FLOP,OCTAL,D TYPE,ALS-TTL,LLCC,20PIN,CERAMIC
SN54ALS273FH-00	TI	获取价格	ALS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20
SN54ALS273FK	TI	获取价格	OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
SN54ALS273J	TI	获取价格	OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
SN54ALS273J-00	TI	获取价格	ALS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CDIP20

与SN54ALS259相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

35
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

27
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

55
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

52

产品中心

服务支持

精选活动

关于我们

帮助中心

SN54ALS259

SN54ALS259 数据手册

SN54ALS259 替代型号

与SN54ALS259相关器件

与SN54ALS259相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN54ALS259

SN54ALS259 数据手册

SN54ALS259 替代型号

与SN54ALS259相关器件

与SN54ALS259相关文章

您还可以找

您在本页遇到什么问题？