Datasheet > SN54ALS29823_15

SN54ALS29823_15

更新时间： 2024-11-27 02:58:35

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
7页	112K
描述
9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN54ALS29823_15 数据手册

SN54ALS29823, SN74ALS29823

9-BIT BUS-INTERFACE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SDAS146B – JANUARY 1986 – REVISED JANUARY 1995

SN54ALS29823 . . . JT PACKAGE

SN74ALS29823 . . . DW OR NT PACKAGE

(TOP VIEW)

• Functionally Equivalent to AMD’s AM29823

• Provide Extra Data Width Necessary for

Wider Address/Data Paths or Buses With

Parity

• Outputs Have Undershoot-Protection

23 1Q

22 2Q

21 3Q

20 4Q

19 5Q

18 6Q

17 7Q

16 8Q

15 9Q

14 CLKEN

13 CLK

Circuitry

• Power-Up High-Impedance State

• Buffered Control Inputs Reduce dc Loading

Effects

• Package Options Include Plastic

Small-Outline (DW) Packages and Standard

Plastic (NT) and Ceramic (JT) 300-mil DIPs

9D 10

CLR 11

GND 12

description

These 9-bit flip-flops feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O

ports, bidirectional bus drivers, parity bus interfacing, and working registers.

With the clock-enable (CLKEN) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high

transitions of the clock (CLK) input. Taking CLKEN high disables the clock buffer, latching the outputs. The

′ALS29823 have noninverting data (D) inputs. Taking the clear (CLR) input low causes the nine Q outputs to

go low independently of the clock.

Abufferedoutput-enable(OE)inputplacesthenineoutputsineitheranormallogicstate(highorlowlogiclevels)

or a high-impedance state. The outputs also are in the high-impedance state during power-up and power-down

conditions. The outputs remain in the high-impedance state while the device is powered down. In the

high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state

and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

The SN54ALS29823 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ALS29823 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLR CLKEN CLK

↑

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

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与SN54ALS29823_15相关器件

型号	品牌	获取价格	描述	数据表
SN54ALS29823JT	TI	获取价格	9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54ALS29824FK	ROCHESTER	获取价格	ALS SERIES, 9-BIT DRIVER, INVERTED OUTPUT, CQCC28
SN54ALS29824JT	ROCHESTER	获取价格	ALS SERIES, 9-BIT DRIVER, INVERTED OUTPUT, CDIP24
SN54ALS29825FK	ROCHESTER	获取价格	ALS SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC28
SN54ALS29825JT	ROCHESTER	获取价格	ALS SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP24, 0.300 INCH, CERAMIC, DIP-24
SN54ALS29826JT	ROCHESTER	获取价格	ALS SERIES, 8-BIT DRIVER, INVERTED OUTPUT, CDIP24
SN54ALS299	TI	获取价格	8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS
SN54ALS299_16	TI	获取价格	8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS
SN54ALS299FH	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,LLCC,20PIN,CERAMIC
SN54ALS299FK	TI	获取价格	8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS

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