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SN54ALS32_15 PDF预览

SN54ALS32_15

更新时间: 2024-11-24 02:58:15
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Package Options Include Plastic

SN54ALS32_15 数据手册

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SN54ALS32, SN54AS32, SN74ALS32, SN74AS32  
QUADRUPLE 2-INPUT POSITIVE-OR GATES  
SDAS113B – APRIL 1982 – REVISED DECEMBER 1994  
SN54ALS32, SN54AS32 . . . J PACKAGE  
SN74ALS32, SN74AS32 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
description  
1Y  
2A  
These devices contain four independent 2-input  
positive-OR gates. They perform the Boolean  
functions Y = A B or Y = A + B in positive logic.  
2B  
2Y  
GND  
8
The  
SN54ALS32  
and  
SN54AS32  
are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS32andSN74AS32arecharacterizedfor  
operation from 0°C to 70°C.  
SN54ALS32, SN54AS32 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
1Y  
NC  
2A  
4
5
6
7
8
4A  
NC  
4Y  
NC  
3B  
INPUTS  
OUTPUT  
Y
17  
16  
15  
14  
A
B
X
H
L
H
X
L
H
H
L
NC  
2B  
9 10 11 12 13  
NC – No internal connection  
logic symbol  
logic diagram (positive logic)  
1
1
1A  
2
1A  
2
3
6
8
1  
3
6
1Y  
2Y  
3Y  
4Y  
1Y  
2Y  
3Y  
4Y  
1B  
1B  
4
4
2A  
5
2A  
5
2B  
9
2B  
3A  
10  
3B  
12  
4A  
13  
4B  
9
3A  
8
10  
3B  
11  
12  
4A  
4B  
11  
13  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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