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SN54ALS32J-00 PDF预览

SN54ALS32J-00

更新时间: 2024-11-23 20:58:07
品牌 Logo 应用领域
德州仪器 - TI 输入元件逻辑集成电路
页数 文件大小 规格书
19页 871K
描述
ALS SERIES, QUAD 2-INPUT OR GATE, CDIP14

SN54ALS32J-00 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.25系列:ALS
JESD-30 代码:R-GDIP-T14长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:OR GATE
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE最大电源电流(ICC):4.9 mA
传播延迟(tpd):13 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

SN54ALS32J-00 数据手册

 浏览型号SN54ALS32J-00的Datasheet PDF文件第2页浏览型号SN54ALS32J-00的Datasheet PDF文件第3页浏览型号SN54ALS32J-00的Datasheet PDF文件第4页浏览型号SN54ALS32J-00的Datasheet PDF文件第5页浏览型号SN54ALS32J-00的Datasheet PDF文件第6页浏览型号SN54ALS32J-00的Datasheet PDF文件第7页 
SN54ALS32, SN54AS32, SN74ALS32, SN74AS32  
QUADRUPLE 2-INPUT POSITIVE-OR GATES  
SDAS113B – APRIL 1982 – REVISED DECEMBER 1994  
SN54ALS32, SN54AS32 . . . J PACKAGE  
SN74ALS32, SN74AS32 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
description  
1Y  
2A  
These devices contain four independent 2-input  
positive-OR gates. They perform the Boolean  
functions Y = A B or Y = A + B in positive logic.  
2B  
2Y  
GND  
8
The  
SN54ALS32  
and  
SN54AS32  
are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS32andSN74AS32arecharacterizedfor  
operation from 0°C to 70°C.  
SN54ALS32, SN54AS32 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
1Y  
NC  
2A  
4
5
6
7
8
4A  
NC  
4Y  
NC  
3B  
INPUTS  
OUTPUT  
Y
17  
16  
15  
14  
A
B
X
H
L
H
X
L
H
H
L
NC  
2B  
9 10 11 12 13  
NC – No internal connection  
logic symbol  
logic diagram (positive logic)  
1
1
1A  
2
1A  
2
3
6
8
1  
3
6
1Y  
2Y  
3Y  
4Y  
1Y  
2Y  
3Y  
4Y  
1B  
1B  
4
4
2A  
5
2A  
5
2B  
9
2B  
3A  
10  
3B  
12  
4A  
13  
4B  
9
3A  
8
10  
3B  
11  
12  
4A  
4B  
11  
13  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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