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SN54ABT543

更新时间： 2024-11-12 12:22:35
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
7页 140K
描述
OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN54ABT543 数据手册

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SCBS157A − JANUARY 1991 − REVISED JULY 1994  
SN54ABT543 . . . JT PACKAGE  
SN74ABT543 . . . DB, DW, OR NT PACKAGE  
(TOP VIEW)  
• State-of-the-Art EPIC-ΙΙBBiCMOS Design  
Significantly Reduces Power Dissipation  
• ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model (C = 200 pF,  
R = 0)  
LEBA  
OEBA  
A1  
1
2
3
4
5
6
7
8
9
10  
24  
V
CC  
23 CEBA  
22 B1  
21 B2  
20 B3  
19 B4  
18 B5  
17 B6  
16 B7  
• Latch-Up Performance Exceeds 500 mA  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Per JEDEC Standard JESD-17  
• Typical V  
(Output Ground Bounce)  
OLP  
CC  
< 1 V at V  
= 5 V, T = 25°C  
A
• High-Drive Outputs (−32-mA I  
,
OH  
64-mA I  
)
OL  
15  
B8  
• Package Options Include Plastic  
CEAB 11  
GND 12  
14 LEAB  
13 OEAB  
Small-Outline (DW) and Shrink  
Small-Outline (DB) Packages, Ceramic  
Chip Carriers (FK), and Plastic (NT) and  
Ceramic (JT) DIPs  
SN54ABT543 . . . FK PACKAGE  
(TOP VIEW)  
description  
The ′ABT543 octal transceivers contain two sets  
of D-type latches for temporary storage of data  
flowing in either direction. Separate latch-enable  
(LEAB or LEBA) and output-enable (OEAB or  
OEBA) inputs are provided for each register to  
permit independent control in either direction of  
data flow.  
4
3
2
1
28 27 26  
25  
5
6
7
8
9
A2  
A3  
A4  
NC  
A5  
B2  
B3  
B4  
NC  
B5  
B6  
B7  
24  
23  
22  
21  
20  
19  
The A-to-B enable (CEAB) input must be low in  
order to enter data from A or to output data from  
B. If CEAB is low and LEAB is low, the A-to-B  
latches are transparent; a subsequent low-to-high  
transition of LEAB puts the A latches in the storage  
mode. With CEAB and OEAB both low, the 3-state  
B outputs are active and reflect the data present  
at the output of the A latches. Data flow from B to  
A is similar but requires using the CEBA, LEBA,  
and OEBA inputs.  
A6 10  
A7 11  
12 13 14 15 16 17 18  
NC − No internal connection  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
The SN74ABT543 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54ABT543 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
SN74ABT543 is characterized for operation from −40°C to 85°C.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1994, Texas Instruments Incorporated  
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2−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567

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