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SN54ABT543AJT

更新时间： 2024-09-22 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
18页 430K
描述
OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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SN54ABT543AJT 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：24
Reach Compliance Code：unknown风险等级：5.84
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION系列：ABT
JESD-30 代码：R-GDIP-T24长度：32.005 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
最大电源电流（ICC）：34 mA传播延迟（tpd）：6.4 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：BICMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm

SN54ABT543AJT 数据手册

 浏览型号SN54ABT543AJT的Datasheet PDF文件第2页浏览型号SN54ABT543AJT的Datasheet PDF文件第3页浏览型号SN54ABT543AJT的Datasheet PDF文件第4页浏览型号SN54ABT543AJT的Datasheet PDF文件第5页浏览型号SN54ABT543AJT的Datasheet PDF文件第6页浏览型号SN54ABT543AJT的Datasheet PDF文件第7页 
SN54ABT543A, SN74ABT543A  
OCTAL REGISTERED TRANSCEIVERS  
WITH 3-STATE OUTPUTS  
SCBS157F – JANUARY 1991 – REVISED MAY 1997  
SN54ABT543A . . . JT OR W PACKAGE  
SN74ABT543A . . . DB, DW, NT, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
LEBA  
OEBA  
A1  
1
2
3
4
5
6
7
8
9
24  
V
CC  
23 CEBA  
22 B1  
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
A2  
A3  
A4  
A5  
A6  
A7  
21 B2  
at V  
= 5 V, T = 25°C  
CC  
A
20 B3  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
19 B4  
Package Options Include Plastic  
18 B5  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Package, and Plastic (NT)  
and Ceramic (JT) DIPs  
17 B6  
16 B7  
A8 10  
CEAB 11  
GND 12  
15 B8  
14 LEAB  
13 OEAB  
description  
SN54ABT543A . . . FK PACKAGE  
(TOP VIEW)  
The ’ABT543A octal transceivers contain two sets  
of D-type latches for temporary storage of data  
flowing in either direction. Separate latch-enable  
(LEAB or LEBA) and output-enable (OEAB or  
OEBA) inputs are provided for each register to  
permit independent control in either direction of  
data flow.  
4
3
2
1
28 27 26  
25  
5
6
7
8
9
A2  
A3  
A4  
NC  
A5  
B2  
B3  
B4  
NC  
B5  
B6  
B7  
24  
23  
22  
21  
20  
19  
The A-to-B enable (CEAB) input must be low to  
enter data from A or to output data from B. If CEAB  
is low and LEAB is low, the A-to-B latches are  
transparent; a subsequent low-to-high transition  
of LEAB puts the A latches in the storage mode.  
With CEAB and OEAB both low, the 3-state  
B outputs are active and reflect the data present  
at the output of the A latches. Data flow from B to  
A is similar, but requires using the CEBA, LEBA,  
and OEBA inputs.  
A6 10  
A7 11  
12 13 14 15 16 17 18  
NC – No internal connection  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
The SN54ABT543A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ABT543A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

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