Datasheet > SN54ABT3614PCBR

SN54ABT3614PCBR

更新时间： 2024-11-15 20:06:15

品牌	Logo	应用领域
德州仪器 - TI		先进先出芯片信息通信管理
页数	文件大小	规格书
44页	683K
描述
64X36 BI-DIRECTIONAL FIFO, 12ns, PQFP120, TQFP-120

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SN54ABT3614PCBR 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	HLFQFP,	针数：	120
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.83
最长访问时间：	12 ns	其他特性：	PARITY GENERATOR/CHECKER, MAILBOX
周期时间：	20 ns	JESD-30 代码：	S-PQFP-G120
长度：	14 mm	内存密度：	2304 bit
内存宽度：	36	功能数量：	1
端子数量：	120	字数：	64 words
字数代码：	64	工作模式：	SYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	64X36	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	HLFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	BICMOS	温度等级：	MILITARY
端子形式：	GULL WING	端子节距：	0.4 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

SN54ABT3614PCBR 数据手册

SN54ABT3614

64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

WITH BUS MATCHING AND BYTE SWAPPING

SGBS308F – AUGUST 1995 – REVISED MAY 2000

Free-Running CLKA and CLKB Can Be

Asynchronous or Coincident

EFB, FFB, AEB, and AFB Flags

Synchronized by CLKB

Two Independent 64 × 36 Clocked FIFOs

Passive Parity Checking on Each Port

Buffering Data in Opposite Directions

Parity Generation Can Be Selected for Each

Port

Mailbox-Bypass Register for Each FIFO

Dynamic Port-B Bus Sizing of 36 Bits (Long

Word), 18 Bits (Word), and 9 Bits (Byte)

Low-Power Advanced BiCMOS Technology

Supports Clock Frequencies up to 50 MHz

Fast Access Times of 12 ns

Selection of Big- or Little-Endian Format for

Word and Byte Bus Sizes

Released as DSCC SMD (Standard

Microcircuit Drawing) 5962-9560901QYA

and 5962-9560901NXD

Three Modes of Byte-Order Swapping on

Port B

Almost-Full and Almost-Empty Flags

Microprocessor Interface Control Logic

Package Options Include 132-Pin Ceramic

Quad Flat (HFP) and 120-Pin Plastic Quad

Flat (PCB) Packages

EFA, FFA, AEA, and AFA Flags

Synchronized by CLKA

description

The SN54ABT3614 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock

frequenciesupto50MHzandhasread-accesstimesasfastas12ns. Twoindependent64× 36dual-portSRAM

FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions

and two programmable flags (almost full and almost empty) to indicate when a selected number of words is

stored in memory. FIFO data on port B can be input and output in 36-bit, 18-bit, and 9-bit formats, with a choice

of big- or little-endian configurations. Three modes of byte-order swapping are possible with any bus-size

selection. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each

mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port

and can be ignored if not desired. Parity generation can be selected for data read from each port.

The SN54ABT3614 is a clocked FIFO, which means each port employs a synchronous interface. All data

transfersthroughaportaregatedtothelow-to-hightransitionofacontinuous(free-running)portclockbyenable

signals. The continuous clocks for each port are independent of one another and can be asynchronous or

coincident. The enables for each port are arranged to provide a simple bidirectional interface between

microprocessors and/or buses controlled by a synchronous interface.

The full flag and almost-full flag of a FIFO are two-stage synchronized to the port clock that writes data to its

array. The empty flag and almost-empty flag of a FIFO are two-stage synchronized to the port clock that reads

data from its array.

The SN54ABT3614 is characterized for operation over the full military temperature range of –55°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...44

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SN54ABT373_16	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54ABT373FK	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54ABT373J	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54ABT373W	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54ABT374	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54ABT374_16	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54ABT374AFK	TI	获取价格	ABT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20
SN54ABT374AJ	TI	获取价格	ABT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20

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