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SN54ABT534AFK PDF预览

SN54ABT534AFK

更新时间: 2024-09-23 13:13:43
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德州仪器 - TI 触发器输出元件
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SN54ABT534AFK 数据手册

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SN54ABT534, SN74ABT534A  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS187F – JANUARY 1991 – REVISED JANUARY 1997  
SN54ABT534 . . . J OR W PACKAGE  
SN74ABT534A . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
Typical V  
(Output Ground Bounce) < 1 V  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
CLK  
OLP  
at V  
= 5 V, T = 25°C  
CC  
A
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Plastic (N) and Ceramic (J) DIPs, and  
Ceramic Flat (W) Package  
GND  
SN54ABT534 . . . FK PACKAGE  
(TOP VIEW)  
description  
3
2 1 20 19  
18  
These 8-bit flip-flops with 3-state outputs are  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
8D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17 7D  
16  
7Q  
15  
6Q  
14  
6D  
9 10 11 12 13  
The eight flip-flops are edge-triggered D-type  
flip-flops. On the positive transition of the clock  
(CLK), the Q outputs are set to the complement of  
the logic levels set up at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without need for interface or pullup components.  
OE does not affect the internal operations of the flip-flop. Previously stored data can be retained or new data  
can be entered while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54ABT534 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74ABT534A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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