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SN54ABT374AW PDF预览

SN54ABT374AW

更新时间： 2024-11-15 20:01:03
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理输出元件逻辑集成电路
页数 文件大小 规格书
21页 1141K
描述
ABT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20

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SN54ABT374AW 技术参数

生命周期：Obsolete包装说明：DFP,
Reach Compliance Code：unknown风险等级：5.29
系列：ABTJESD-30 代码：R-GDFP-F20
长度：13.09 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK最大电源电流（ICC）：30 mA
传播延迟（tpd）：7.6 ns认证状态：Not Qualified
座面最大高度：2.54 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BICMOS
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
宽度：6.92 mmBase Number Matches：1

SN54ABT374AW 数据手册

 浏览型号SN54ABT374AW的Datasheet PDF文件第2页浏览型号SN54ABT374AW的Datasheet PDF文件第3页浏览型号SN54ABT374AW的Datasheet PDF文件第4页浏览型号SN54ABT374AW的Datasheet PDF文件第5页浏览型号SN54ABT374AW的Datasheet PDF文件第6页浏览型号SN54ABT374AW的Datasheet PDF文件第7页 
SN54ABT374, SN74ABT374A  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCBS111G – FEBRUARY 1991 – REVISED JANUARY 1997  
SN54ABT374 . . . J OR W PACKAGE  
SN74ABT374A . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
Typical V  
(Output Ground Bounce) < 1 V  
8Q  
8D  
7D  
OLP  
at V  
= 5 V, T = 25°C  
CC  
A
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
16 7Q  
15 6Q  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
14  
13  
12  
11  
6D  
5D  
5Q  
CLK  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Plastic (N) and Ceramic (J) DIPs, and  
Ceramic Flat (W) Package  
GND  
SN54ABT374 . . . FK PACKAGE  
(TOP VIEW)  
description  
3
2
1
20 19  
18  
These 8-bit flip-flops feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
4
5
6
7
8
17  
16  
15  
14 6D  
9 10 11 12 13  
The eight flip-flops of the SN54ABT374 and  
SN74ABT374A are edge-triggered D-type  
flip-flops. On the positive transition of the clock  
(CLK) input, the Q outputs are set to the logic  
levels set up at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data  
can be retained or new data can be entered while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54ABT374 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74ABT374A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

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与SN54ABT374AW相关器件

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SN54ABT374FK TI

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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54ABT374J TI

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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54ABT374W TI

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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54ABT377 TI

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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SN54ABT377FK TI

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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SN54ABT377J TI

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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SN54ABT377W TI

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 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SN54ABT533 TI

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 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN54ABT533_16 TI

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 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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