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SCBS094B − DECEMBER 1991 − JULY 1994
SN54ABT5400 . . . JT PACKAGE
SN74ABT5400 . . . DW PACKAGE
(TOP VIEW)
• Output Ports Have 25-Ω Series Resistors,
So No External Resistors Are Required
• State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Y1
Y2
Y3
Y4
Y5
D1
D2
D3
D4
D5
D6
V
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
• Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
• Typical V
(Output Ground Bounce)
OLP
CC
< 1 V at V
= 5 V, T = 25°C
A
• Typical V
(Output Undershoot)
Y6
OLV
< 0.5 V at V
= 5 V, T = 25°C
GND
GND
Y7
CC
A
CC
V
• Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK) and DIPs (JT)
CC
D7
Y8 10
19 D8
Y9
Y10
D9
D10
11
12
18
17
description
Y11 13
OE1 14
16 D11
15 OE2
These 11-bit buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters.
SN54ABT5400 . . . FK PACKAGE
(TOP VIEW)
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1 or OE2) input is high, all 11 outputs are in the
high-impedance state.
4
3
2
1
28 27 26
25
5
6
7
8
9
D3
D2
D1
Y1
Y2
Y3
Y4
D9
D10
D11
24
23
The outputs, which are designed to source or sink
up to 12 mA, include 25-Ω series resistors to
reduce overshoot and undershoot.
22 OE2
21 OE1
20 Y11
19 Y10
10
11
To ensure the high-impedance state during power
up or power down, OE should be tied to V
CC
1213 14 15 16 17 18
through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking
capability of the driver.
The SN54ABT5400 is characterized for operation
over the full military temperature range of −55°C
to 125°C. The SN74ABT5400 is characterized for
operation from −40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
Y
OE1
L
OE2
L
D
L
L
L
L
H
X
X
H
Z
Z
H
X
X
H
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
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6−1
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