Datasheet > SN54ABT374_16

SN54ABT374_16

更新时间： 2024-09-24 02:58:27

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
7页	111K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN54ABT374_16 数据手册

SN54ABT374, SN74ABT374A

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCBS111G – FEBRUARY 1991 – REVISED JANUARY 1997

SN54ABT374 . . . J OR W PACKAGE

SN74ABT374A . . . DB, DW, N, OR PW PACKAGE

(TOP VIEW)

State-of-the-Art EPIC-ΙΙB BiCMOS Design

Significantly Reduces Power Dissipation

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical V

(Output Ground Bounce) < 1 V

OLP

at V

= 5 V, T = 25°C

High-Drive Outputs (–32-mA I , 64-mA I

)

16 7Q

15 6Q

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

CLK

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Plastic (N) and Ceramic (J) DIPs, and

Ceramic Flat (W) Package

GND

SN54ABT374 . . . FK PACKAGE

(TOP VIEW)

description

20 19

These 8-bit flip-flops feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. They are

particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

14 6D

9 10 11 12 13

The eight flip-flops of the SN54ABT374 and

SN74ABT374A are edge-triggered D-type

flip-flops. On the positive transition of the clock

(CLK) input, the Q outputs are set to the logic

levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive

thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines

without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data

can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT374 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74ABT374A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

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与SN54ABT374_16相关器件

型号	品牌	获取价格	描述	数据表
SN54ABT374AFK	TI	获取价格	ABT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20
SN54ABT374AJ	TI	获取价格	ABT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20
SN54ABT374AW	TI	获取价格	ABT SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDFP20
SN54ABT374FK	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54ABT374J	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54ABT374W	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN54ABT377	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SN54ABT377_16	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SN54ABT377FK	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
SN54ABT377J	TI	获取价格	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLOCK ENABLE

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