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SN54ABT18245A_06

更新时间： 2024-10-01 05:18:27
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德州仪器 - TI 总线收发器测试
页数 文件大小 规格书
32页 436K
描述
SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS

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SN54ABT18245A_06 数据手册

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SN54ABT18245A, SN74ABT18245A  
SCAN TEST DEVICES  
WITH 18-BIT BUS TRANSCEIVERS  
SCBS110H – AUGUST 1992 – REVISED FEBRUARY 1999  
SN54ABT18245A . . . WD PACKAGE  
SN74ABT18245A . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
SCOPE Family of Testability Products  
Members of the Texas Instruments  
Widebus Family  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1
56 1OE  
Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port and  
Boundary-Scan Architecture  
2
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1A1  
1A2  
GND  
1A3  
1A4  
3
4
SCOPE Instruction Set  
5
– IEEE Standard 1149.1-1990 Required  
Instructions, CLAMP and HIGHZ  
– Parallel-Signature Analysis at Inputs  
– Pseudo-Random Pattern Generation  
From Outputs  
– Sample Inputs/Toggle Outputs  
– Binary Count From Outputs  
– Device Identification  
6
7
V
V
CC  
CC  
8
1B5  
1B6  
1B7  
GND  
1B8  
1B9  
2B1  
2B2  
2B3  
2B4  
GND  
2B5  
2B6  
2B7  
1A5  
1A6  
1A7  
GND  
1A8  
1A9  
2A1  
2A2  
2A3  
2A4  
GND  
2A5  
2A6  
2A7  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
– Even-Parity Opcodes  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Packaged in Plastic Shrink Small-Outline  
(DL) and Thin Shrink Small-Outline (DGG)  
Packages and 380-mil Fine-Pitch Ceramic  
Flat (WD) Packages  
description  
V
V
CC  
CC  
2B8  
2B9  
GND  
2DIR  
TDO  
TMS  
2A8  
2A9  
GND  
2OE  
TDI  
The’ABT18245Ascantestdeviceswith18-bitbus  
transceivers are members of the Texas  
Instruments SCOPE  
testability integrated-  
circuit family. This family of devices supports IEEE  
Standard 1149.1-1990 boundary scan to facilitate  
testing of complex circuit-board assemblies. Scan  
access to the test circuitry is accomplished via the  
4-wire test access port (TAP) interface.  
TCK  
In the normal mode, these devices are 18-bit noninverting bus transceivers. They can be used either as two  
9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot  
samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating  
the TAP in the normal mode does not affect the functional operation of the SCOPE bus transceivers.  
Data flow is controlled by the direction-control (DIR) and output-enable (OE) inputs. Data transmission is  
allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE can  
be used to disable the device so that the buses are effectively isolated.  
In the test mode, the normal operation of the SCOPE bus transceivers is inhibited and the test circuitry is  
enabled to observe and control the input/output (I/O) boundary of the device. When enabled, the test circuitry  
performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE, Widebus, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...32

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