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SN54ABT18504HVR PDF预览

SN54ABT18504HVR

更新时间: 2024-10-01 13:13:43
品牌 Logo 应用领域
德州仪器 - TI 总线收发器测试
页数 文件大小 规格书
30页 450K
描述
ABT SERIES, 20-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68

SN54ABT18504HVR 技术参数

生命周期:Obsolete包装说明:QFF,
Reach Compliance Code:unknown风险等级:5.84
其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; WITH CLOCK ENABLE系列:ABT
JESD-30 代码:S-GQFP-F68长度:12.51 mm
负载电容(CL):50 pF逻辑集成电路类型:BOUNDARY SCAN REG BUS TRANSCEIVER
位数:20功能数量:1
端口数量:2端子数量:68
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:QFF
封装形状:SQUARE封装形式:FLATPACK
最大电源电流(ICC):40 mA传播延迟(tpd):7.1 ns
认证状态:Not Qualified座面最大高度:3.86 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:BICMOS温度等级:MILITARY
端子形式:FLAT端子节距:0.635 mm
端子位置:QUAD宽度:12.51 mm
Base Number Matches:1

SN54ABT18504HVR 数据手册

 浏览型号SN54ABT18504HVR的Datasheet PDF文件第2页浏览型号SN54ABT18504HVR的Datasheet PDF文件第3页浏览型号SN54ABT18504HVR的Datasheet PDF文件第4页浏览型号SN54ABT18504HVR的Datasheet PDF文件第5页浏览型号SN54ABT18504HVR的Datasheet PDF文件第6页浏览型号SN54ABT18504HVR的Datasheet PDF文件第7页 
SN54ABT18504, SN74ABT18504  
SCAN TEST DEVICES WITH  
20-BIT UNIVERSAL BUS TRANSCEIVERS  
SCBS108B – AUGUST 1992 – REVISED JUNE 1993  
Members of the Texas Instruments  
SCOPE Instruction Set  
– IEEE Standard 1149.1-1990 Required  
Instructions, Optional INTEST, and  
P1149.1A CLAMP and HIGHZ  
– Parallel Signature Analysis at Inputs With  
Masking Option  
SCOPE Family of Testability Products  
Members of the Texas Instruments  
Widebus Family  
Compatible With the IEEE Standard  
1149.1-1990 (JTAG) Test Access Port and  
Boundary-Scan Architecture  
– Pseudo-Random Pattern Generation  
From Outputs  
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
– Sample Inputs/Toggle Outputs  
– Binary Count From Outputs  
– Device Identification  
– Even-Parity Opcodes  
Two Boundary-Scan Cells per I/O for  
Packaged in 64-Pin Plastic Thin Quad Flat  
Pack Using 0.5-mm Center-to-Center  
Spacings and 68-Pin Ceramic Quad Flat  
Pack Using 25-mil Center-to-Center  
Spacings  
Greater Flexibility  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
SN54ABT18504 . . . HV PACKAGE  
(TOP VIEW)  
9
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2 1 68 67 66 65 64 63 62 61  
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A4  
A5  
A6  
GND  
A7  
A8  
A9  
A10  
NC  
B5  
B6  
B7  
GND  
B8  
B9  
B10  
V
CC  
NC  
V
B11  
B12  
B13  
B14  
GND  
B15  
B16  
B17  
CC  
A11  
A12  
A13  
GND  
A14  
A15  
A16  
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  
NC – No internal connection  
SCOPE, Widebus, UBT, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1993, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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