Datasheet > SN54ABT18652

SN54ABT18652

更新时间： 2024-11-13 22:39:39

品牌	Logo	应用领域
德州仪器 - TI		总线收发器测试
页数	文件大小	规格书
11页	171K
描述
SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS

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SN54ABT18652 数据手册

SN54ABT18652, SN74ABT18652

SCAN TEST DEVICES WITH

18-BIT BUS TRANSCEIVERS AND REGISTERS

SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992

• Members of the Texas Instruments

• SCOPE Instruction Set

– IEEE Standard 1149.1-1990 Required

Instructions, Optional INTEST, and

P1149.1A CLAMP and HIGHZ

– Parallel Signature Analysis at Inputs With

Masking Option

SCOPE Family of Testability Products

• Members of the Texas Instruments

Widebus Family

• Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and

Boundary-Scan Architecture

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

• Include D-Type Flip-Flops and Control

Circuitry to Provide Multiplexed

Transmission of Stored and Real-Time Data

• Two Boundary-Scan Cells per I/O for

– Even-Parity Opcodes

Greater Flexibility

• Packaged in 64-Pin Plastic Shrink Quad Flat

Pack (PM) and 68-Pin Ceramic Quad Flat

Pack (HV)

• State-of-the-Art EPIC-ΙΙB BiCMOS Design

Significantly Reduces Power Dissipation

SN54ABT18652 . . . HV PACKAGE

(TOP VIEW)

68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52

1A3

1A4

1A5

GND

1A6

1A7

1A8

1A9

1B4

1B5

1B6

GND

1B7

1B8

1B9

2B1

2B2

2B3

2B4

GND

2B5

2B6

2B7

2A1

2A2

2A3

GND

2A4

2A5

2A6

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

NC – No internal connection

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...11

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与SN54ABT18652相关器件

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