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SN54ABT16843 PDF预览

SN54ABT16843

更新时间： 2024-11-13 23:06:07
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德州仪器 - TI 锁存器输出元件
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8页 135K
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18-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN54ABT16843 数据手册

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SN54ABT16843, SN74ABT16843  
18-BIT BUS-INTERFACE D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCBS223E – OCTOBER 1992 – REVISED MAY 1997  
SN54ABT16843 . . . WD PACKAGE  
SN74ABT16843 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1
56  
55  
54  
53  
52  
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50  
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48  
47  
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45  
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43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1CLR  
1OE  
1Q1  
GND  
1Q2  
1Q3  
1LE  
1PRE  
1D1  
GND  
1D2  
1D3  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
2
CC  
3
4
Flow-Through Architecture Optimizes PCB  
Layout  
5
6
High-Impedance State During Power Up  
and Power Down  
7
V
V
CC  
CC  
8
1Q4  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
1Q9  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
1D4  
1D5  
1D6  
GND  
1D7  
1D8  
1D9  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
9
Package Options Include Plastic Thin  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Shrink Small-Outline (DGG), 300-mil Shrink  
Small-Outline (DL) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
The ’ABT16843 18-bit bus-interface D-type  
latches are designed specifically for driving highly  
capacitive or relatively low-impedance loads.  
They are particularly suitable for implementing  
buffer registers, I/O ports, bidirectional bus  
drivers, and working registers.  
V
V
CC  
CC  
2Q7  
2Q8  
GND  
2Q9  
2OE  
2CLR  
2D7  
2D8  
GND  
2D9  
2PRE  
2LE  
The ’ABT16843 can be used as two 9-bit latches  
or one 18-bit latch. The 18 latches are transparent  
D-type latches. The device provides true data at  
its outputs.  
A buffered output-enable (OE) input can be used  
to place the nine outputs in either a normal logic  
state (high or low logic levels) or  
a
high-impedance state. The outputs are in the  
high-impedance state during power up and power  
down. The outputs remain in the high-impedance  
state while the device is powered down. In the  
high-impedance state, the outputs neither load  
nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
need for interface or pullup components.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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