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SN54ABT16853 PDF预览

SN54ABT16853

更新时间： 2024-11-13 23:06:07
品牌 Logo 应用领域
德州仪器 - TI 总线收发器
页数 文件大小 规格书
8页 145K
描述
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS

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SN54ABT16853 数据手册

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SN54ABT16853, SN74ABT16853  
DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS  
SCBS153B – OCTOBER 1992 – REVISED JANUARY 1997  
SN54ABT16853 . . . WD PACKAGE  
SN74ABT16853 . . . DGG OR DL PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
Widebus Family  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1OEB  
1LE  
1ERR  
GND  
1A1  
1OEA  
1CLR  
1PARITY  
GND  
1B1  
1B2  
Latch-Up Performance Exceeds 500 mA  
Per JEDEC Standard JESD-17  
2
3
4
Typical V  
(Output Ground Bounce) < 1 V  
OLP  
5
at V  
= 5 V, T = 25°C  
CC  
A
6
1A2  
Distributed V  
Minimizes High-Speed Switching Noise  
and GND Pin Configuration  
CC  
7
V
V
CC  
CC  
8
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
Flow-Through Architecture Optimizes  
PCB Layout  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
Parity-Error Flag With Parity  
Generator/Checker  
Latch for Storage of the Parity-Error Flag  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages and 380-mil  
Fine-Pitch Ceramic Flat (WD) Package  
Using 25-mil Center-to-Center Spacings  
description  
V
V
CC  
CC  
The ’ABT16853 dual 8-bit to 9-bit parity  
transceivers are designed for communication  
between data buses. When data is transmitted  
from the A bus to the B bus, a parity bit is  
generated. When data is transmitted from the  
B bus to the A bus, with its corresponding parity  
bit, the open-collector parity-error (ERR) output  
indicates whether or not an error in the B data has  
occurred. The output-enable (OEA and OEB)  
inputs can be used to disable the device so that  
the buses are effectively isolated. The ’ABT16853  
provide true data at the outputs.  
2A7  
2A8  
GND  
2ERR  
2LE  
2B7  
2B8  
GND  
2PARITY  
2CLR  
2OEA  
2OEB  
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports  
with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the  
latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from  
the A bus to the B bus, and inverted parity is generated. Inverted parity is a forced error condition that gives the  
designer more system diagnostic capability.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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