ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢃ
ꢊ ꢋꢌ ꢍꢀ ꢎꢏꢐ ꢑꢒ ꢌꢎ ꢏꢀ ꢓꢎ ꢐꢎ ꢀꢍꢋ ꢂꢎ ꢐ ꢏꢍꢋ ꢒꢔ ꢌ ꢆꢕ ꢂ ꢂꢌ ꢔ
SPRS186L − DECEMBER 2001 − REVISED NOVEMBER 2005
D
D
Highest-Performance Floating-Point Digital
Signal Processor (DSP)
− Eight 32-Bit Instructions/Cycle
− 32/64-Bit Data Word
− 225-, 200-MHz (GDP), and 200-, 167-MHz
(PYP) Clock Rates
− 4.4-, 5-, 6-Instruction Cycle Times
− 1800/1350, 1600/1200, and 1336/1000
MIPS/MFLOPS
D
Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
D
16-Bit Host-Port Interface (HPI)
D
Two McASPs
− Two Independent Clock Zones Each
(1 TX and 1 RX)
− Eight Serial Data Pins Per Port:
Individually Assignable to any of the
Clock Zones
− Each Clock Zone Includes:
− Programmable Clock Generator
− Programmable Frame Sync Generator
− TDM Streams From 2-32 Time Slots
− Support for Slot Size:
8, 12, 16, 20, 24, 28, 32 Bits
− Data Formatter for Bit Manipulation
− Wide Variety of I2S and Similar Bit
Stream Formats
− Integrated Digital Audio Interface
Transmitter (DIT) Supports:
− S/PDIF, IEC60958-1, AES-3, CP-430
Formats
− Rich Peripheral Set, Optimized for Audio
− Highly Optimized C/C++ Compiler
− Extended Temperature Devices Available
Advanced Very Long Instruction Word
(VLIW) TMS320C67x DSP Core
− Eight Independent Functional Units:
− Two ALUs (Fixed-Point)
− Four ALUs (Floating- and Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
− Up to 16 transmit pins
D
D
Instruction Set Features
− Enhanced Channel Status/User Data
− Extensive Error Checking and Recovery
− Native Instructions for IEEE 754
− Single- and Double-Precision
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation; Bit-Field Extract, Set, Clear;
Bit-Counting; Normalization
2
D
D
Two Inter-Integrated Circuit Bus (I C Bus)
Multi-Master and Slave Interfaces
Two Multichannel Buffered Serial Ports:
− Serial-Peripheral-Interface (SPI)
− High-Speed TDM Interface
− AC97 Interface
L1/L2 Memory Architecture
− 4K-Byte L1P Program Cache
(Direct-Mapped)
− 4K-Byte L1D Data Cache (2-Way)
− 256K-Byte L2 Memory Total: 64K-Byte
L2 Unified Cache/Mapped RAM, and
192K-Byte Additional L2 Mapped RAM
D
D
D
D
D
Two 32-Bit General-Purpose Timers
Dedicated GPIO Module With 16 pins
(External Interrupt Capable)
Flexible Phase-Locked-Loop (PLL) Based
Clock Generator Module
†
D
D
Device Configuration
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian
IEEE-1149.1 (JTAG )
Boundary-Scan-Compatible
208-Pin PowerPAD Plastic (Low-Profile)
Quad Flatpack (PYP)
32-Bit External Memory Interface (EMIF)
− Glueless Interface to SRAM, EPROM,
Flash, SBSRAM, and SDRAM
− 512M-Byte Total Addressable External
Memory Space
D
272-BGA Packages (GDP)
D
0.13-µm/6-Level Copper Metal Process
− CMOS Technology
‡
D
3.3-V I/Os, 1.2-V Internal (GDP & PYP)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C67x and PowerPAD are trademarks of Texas Instruments.
2
I C Bus is a trademark of Philips Electronics N.V. Corporation
All trademarks are the property of their respective owners.
†
‡
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26−V designs.
ꢒꢔ ꢌ ꢓꢖ ꢆ ꢀꢎ ꢌ ꢏ ꢓ ꢍꢀꢍ ꢗꢘ ꢙ ꢚꢛ ꢜ ꢝꢞ ꢗꢚꢘ ꢗꢟ ꢠꢡ ꢛ ꢛ ꢢꢘꢞ ꢝꢟ ꢚꢙ ꢣꢡꢤ ꢥꢗꢠ ꢝꢞ ꢗꢚꢘ ꢦꢝ ꢞꢢ ꢧ
ꢒꢛ ꢚ ꢦꢡꢠ ꢞ ꢟ ꢠ ꢚꢘ ꢙꢚ ꢛ ꢜ ꢞ ꢚ ꢟ ꢣꢢ ꢠ ꢗꢙ ꢗꢠꢝ ꢞꢗ ꢚꢘꢟ ꢣꢢ ꢛ ꢞꢨ ꢢ ꢞꢢ ꢛ ꢜꢟ ꢚꢙ ꢀꢢꢩ ꢝꢟ ꢎꢘꢟ ꢞꢛ ꢡꢜ ꢢꢘꢞ ꢟ
ꢟ ꢞ ꢝ ꢘꢦ ꢝ ꢛꢦ ꢪ ꢝ ꢛꢛ ꢝ ꢘ ꢞꢫꢧ ꢒꢛ ꢚ ꢦꢡꢠ ꢞꢗꢚꢘ ꢣꢛ ꢚꢠ ꢢꢟ ꢟꢗ ꢘꢬ ꢦꢚꢢ ꢟ ꢘꢚꢞ ꢘꢢ ꢠꢢ ꢟꢟ ꢝꢛ ꢗꢥ ꢫ ꢗꢘꢠ ꢥꢡꢦ ꢢ
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ
Copyright 2005, Texas Instruments Incorporated
1
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