Datasheet > 微控制器和处理器 > 数字信号处理器> SM320C6201-EP

SM320C6201-EP

更新时间： 2024-11-24 11:58:19

品牌	Logo	应用领域
德州仪器 - TI		数字信号处理器
页数	文件大小	规格书
59页	876K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SM320C6201-EP 数据手册

SM320C6201-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SGUS041A -- MAY 2003 -- REVISED JANUARY 2004

Controlled Baseline

-- One Assembly/Test Site, One Fabrication

Site

1M-Bit On-Chip SRAM

-- 512K-Bit Internal Program/Cache

(16K 32-Bit Instructions)

-- 512K-Bit Dual-Access Internal Data

(64K Bytes) Organized as Two Blocks for

Improved Concurrency

Extended Temperature Performance of

-- 4 0 °C to 105°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

32-Bit External Memory Interface (EMIF)

-- Glueless Interface to Asynchronous

Memories: SRAM and EPROM

-- Glueless Interface to Synchronous

Memories: SDRAM and SBSRAM

Enhanced Product-Change Notification

Qualification Pedigree^†

High-Performance Fixed-Point Digital

Signal Processor (DSP) SM320C6201

-- 5-ns Instruction Cycle Time

-- 200-MHz Clock Rate

-- Eight 32-Bit Instructions/Cycle

-- 1600 MIPS

Four-Channel Bootloading

Direct-Memory-Access (DMA) Controller

with an Auxiliary Channel

16-Bit Host-Port Interface (HPI)

-- Access to Entire Memory Map

VelociTI™ Advanced Very Long Instruction

Word (VLIW) TMS320C62x™ DSP CPU Core

-- Eight Independent Functional Units:

-- Six Arithmetic Logic Units (ALUs)

(32-/40-Bit)

-- Two 16-Bit Multipliers (32-Bit Results)

-- Load-Store Architecture With 32 32-Bit

General-Purpose Registers

Two Multichannel Buffered Serial Ports

(McBSPs)

-- Direct Interface to T1/E1, MVIP, SCSA

Framers

-- ST-Bus-Switching Compatible

-- Up to 256 Channels Each

-- AC97-Compatible

-- Serial Peripheral Interface (SPI)

Compatible (Motorola™)

-- Instruction Packing Reduces Code Size

-- All Instructions Conditional

Two 32-Bit General-Purpose Timers

Instruction Set Features

-- Byte-Addressable (8-, 16-, 32-Bit Data)

-- 32-Bit Address Range

-- 8-Bit Overflow Protection

-- Saturation

Flexible Phase-Locked Loop (PLL) Clock

Generator

IEEE-1149.1 (JTAG^‡) Boundary-Scan

Compatible

-- Bit-Field Extract, Set, Clear

-- Bit-Counting

-- Normalization

352-Pin BGA Package (GJC Suffix)

CMOS Technology

-- 0.18-μm/5-Level Metal Process

3.3-V I/Os, 1.8-V Internal

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

VelociTI and TMS320C62x are trademarks of Texas Instruments.

Motorola is a trademark of Motorola, Inc.

†

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.

This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,

electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this

component beyond specified performance and environmental limits.

‡

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443

12 3 4 5 6 7...59

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