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SM320C6201B PDF预览

SM320C6201B

更新时间： 2024-11-19 22:07:07
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
62页 867K
描述
DIGITAL SIGNAL PROCESSOR

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SM320C6201B 数据手册

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SM J 32 0C 62 01 B  
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SGUS031 – APRIL 2000  
GLP  
D
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Highest Performance Fixed-Point Digital  
Signal Processor (DSP) SM/SMJ320C6201B  
– 5-, 6.7-ns Instruction Cycle Time  
– 150 and 200-MHz Clock Rate  
– Eight 32-Bit Instructions/Cycle  
– 1200 and 1600 MIPS  
429-PIN BALL GRID ARRAY (BGA) PACKAGE  
(BOTTOM VIEW)  
AA  
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VelociTI Advanced Very Long Instruction  
Word (VLIW) ’C62x CPU Core  
– Eight Independent Functional Units:  
– Six ALUs (32-/40-Bit)  
– Two 16-Bit Multipliers (32-Bit Results)  
– Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
E
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B
A
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Instruction Set Features  
– Byte-Addressable (8-, 16-, 32-Bit Data)  
– 32-Bit Address Range  
– 8-Bit Overflow Protection  
– Saturation  
1
3
5
7
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11 13 15 17 19 21  
10 12 14 16 18 20  
2
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– Bit-Field Extract, Set, Clear  
– Bit-Counting  
– Normalization  
D
Two Multichannel Buffered Serial Ports  
(McBSPs)  
– Direct Interface to T1/E1, MVIP, SCSA  
Framers  
D
D
1M-Bit On-Chip SRAM  
– 512K-Bit Internal Program/Cache  
(16K 32-Bit Instructions)  
– 512K-Bit Dual-Access Internal Data  
(64K Bytes) Organized as Two Blocks for  
Improved Concurrency  
– ST-Bus-Switching Compatible  
– Up to 256 Channels Each  
– AC97-Compatible  
– Serial Peripheral Interface (SPI)  
Compatible (Motorola )  
32-Bit External Memory Interface (EMIF)  
– Glueless Interface to Synchronous  
Memories: SDRAM and SBSRAM  
– Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
D
D
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Two 32-Bit General-Purpose Timers  
Flexible Phase-Locked Loop (PLL) Clock  
Generator  
†
IEEE-1149.1 (JTAG ) Boundary-Scan  
Compatible  
D
D
Four-Channel Bootloading  
Direct-Memory-Access (DMA) Controller  
with an Auxiliary Channel  
D
429-Pin BGA Package (GLP Suffix)  
D
CMOS Technology  
– 0.18-µm/5-Level Metal Process  
16-Bit Host-Port Interface (HPI)  
– Access to Entire Memory Map  
D
3.3-V I/Os, 1.8-V Internal  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
VelociTI is a trademark of Texas Instruments Incorporated.  
Motorola is a trademark of Motorola, Inc.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 2000, Texas Instruments Incorporated  
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
1234567...62

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