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SM320C6201

更新时间： 2024-11-23 22:07:07
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德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
73页 1091K
描述
DIGITAL SIGNAL PROCESSORS

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SM320C6201 数据手册

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SM320C6201, SMJ320C6201B  
DIGITAL SIGNAL PROCESSORS  
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999  
GLE and GLP PACKAGES  
(BOTTOM VIEW)  
Highest Performance Fixed-Point Digital  
Signal Processor (DSP) SM320C6201  
– 6.67-ns Instruction Cycle Time  
– 150-MHz Clock Rate  
– Eight 32-Bit Instructions/Cycle  
– 1200 MIPS  
AA  
Y
W
V
U
T
R
P
N
M
L
Highest Performance Fixed-Point Digital  
Signal Processor (DSP) SMJ320C6201B  
– 6.67-ns Instruction Cycle Time  
– 150-MHz Clock Rate  
K
J
H
G
F
E
D
C
B
A
– Eight 32-Bit Instructions/Cycle  
– 1200 MIPS  
VelociTI Advanced Very Long Instruction  
Word (VLIW) ’C6200 CPU Core  
– Eight Independent Functional Units:  
– Six ALUs (32-/40-Bit)  
– Two 16-Bit Multipliers (32-Bit Results)  
– Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
1
3
5
7
9
11 13 15 17 19 21  
10 12 14 16 18 20  
2
4
6
8
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
16-Bit Host-Port Interface (HPI)  
– Access to Entire Memory Map  
Instruction Set Features  
– Byte-Addressable (8-, 16-, 32-Bit Data)  
– 32-Bit Address Range  
– 8-Bit Overflow Protection  
– Saturation  
– Bit-Field Extract, Set, Clear  
– Bit-Counting  
– Normalization  
Two Multichannel Buffered Serial Ports  
(McBSPs)  
– Direct Interface to T1/E1, MVIP, SCSA  
Framers  
– ST-Bus-Switching Compatible  
– Up to 256 Channels Each  
– AC97-Compatible  
– Serial Peripheral Interface (SPI)  
Compatible (Motorola )  
1M-Bit On-Chip SRAM  
– 512K-Bit Internal Program/Cache  
(16K 32-Bit Instructions)  
Two 32-Bit General-Purpose Timers  
Flexible Phase-Locked Loop (PLL) Clock  
Generator  
– 512K-Bit Dual-Access Internal Data  
(64K Bytes) Organized as a Single Block  
(’6201)  
†
IEEE-1149.1 (JTAG ) Boundary-Scan  
– 512K-Bit Dual-Access Internal Data  
(64K Bytes) Organized as Two Blocks for  
Improved Concurrency (’6201B)  
Compatible  
429-Pin BGA Package (GLE Suffix) (’6201)  
429-Pin BGA Package (GLP Suffix) (’6201B)  
32-Bit External Memory Interface (EMIF)  
– Glueless Interface to Synchronous  
Memories: SDRAM and SBSRAM  
– Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
CMOS Technology  
– 0.25-µm/5-Level Metal Process (’6201)  
– 0.18-µm/5-Level Metal Process (’6201B)  
3.3-V I/Os, 2.5-V Internal (’6201)  
3.3-V I/Os, 1.8-V Internal (’6201B)  
Four-Channel Bootloading  
Direct-Memory-Access (DMA) Controller  
with an Auxiliary Channel  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
VelociTI is a trademark of Texas Instruments Incorporated.  
Motorola is a trademark of Motorola, Inc.  
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 1998, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443  
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