Datasheet > SII141B

SII141B

更新时间： 2024-11-28 22:21:51

品牌	Logo	应用领域
其他 - ETC		接收机
页数	文件大小	规格书
12页	86K
描述
SiI 141B PanelLink Digital Receiver

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中文翻译

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SII141B 数据手册

SiI 141B PanelLink^®Digital Receiver

General Description

May 2001

Features

The SiI 141B uses PanelLink Digital technology to support displays

ranging from VGA to High Refresh XGA (25-86 MHz), which is ideal for LCD

desktop monitor applications. With a flexible single or dual pixel out interface

and selectable output drive, the SiI 141B receiver supports up to true color

panels (24 bit/pixel, 16.7M colors) in 1 pixel/clock mode (18 bit/pixel in 2

pixel/clock mode). PanelLink also features an inter-pair skew tolerance up to

1 full input clock cycle. The SiI 141B is pin for pin compatible with the SiI

141 but incorporates a number of enhancements. These include an

improved jitter tolerant PLL design, new HSYNC filter and power down when

the clock is inactive. All PanelLink products are designed on a scaleable

CMOS architecture to support future performance requirements while

maintaining the same logical interface. System designers can be assured

that the interface will be fixed through a number of technology and

performance generations.

•

Scaleable Bandwidth: 25-86 MHz (VGA to High

Refresh XGA)

Low Power: 3.3V core operation & power-down mode

Automatic power down when clock is inactive

High Skew Tolerance: 1 full input clock cycle (15ns at

65 MHz)

Pin-compatible with SiI 101, SiI 141

Sync Detect: for Plug & Display “Hot Plugging”

Cable Distance Support: over 5m with twisted-pair,

fiber-optics ready

•

Compliant with DVI 1.0 (DVI is backwards compatible

with VESA® P&D^TMand DFP)

PanelLink Digital technology simplifies PC design by resolving many of

the system level issues associated with high-speed digital design, providing

the system designer with a digital interface solution that is quicker to market

and lower in cost.

SiI 141B Pin Diagram

24-bit Input Data for 1-pixel/clock mode

8-bit Channel 1 Data

8-bit Channel 2 Data

8-bit Channel 0 Data

1-pixel/clock

18-bit Even Data for 2-pixel/clock mode

6-bit Odd Channel 0

Data 2-pixel/clock

6-bit Even Channel 2

Data 2-pixel/clock

6-bit Even Channel 1

Data 2-pixel/clock

Q20

Q21

Q22

Q23

OGND

Q24

OVCC

VSYNC

OGND

HSYNC

GND

CTL3

CTL2

CTL1

SCDT

DFO

OVCC

Q25

SiI141B

VCC

Q26

80-Pin TQFP

(Top View)

Q27

Q28

Q29

Q30

Q31

PIXS

OGND

PDO

Q32

Q33

Q34

RESERVED

Q35

DIFFERENTIAL SIGNAL

MISC.

Subject to Change without Notice

12 3 4 5 6 7...12

中文翻译

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与SII141B相关器件

型号	品牌	获取价格	描述	数据表
SII145S12	SIRECTIFIER	获取价格	绝缘栅双极型晶体管（IGBT）Isolated Gate Bipolar Transist
SII150A	ETC	获取价格	PanelLink Digital Transmitter
SII150ACT100	ETC	获取价格	PanelLink Digital Transmitter
SII150N06	SIRECTIFIER	获取价格	绝缘栅双极型晶体管（IGBT）Isolated Gate Bipolar Transist
SII150N12	SIRECTIFIER	获取价格	绝缘栅双极型晶体管（IGBT）Isolated Gate Bipolar Transist
SII150S12	SIRECTIFIER	获取价格	绝缘栅双极型晶体管（IGBT）Isolated Gate Bipolar Transist
SII161A	ETC	获取价格	SiI 161A PanelLink Receiver
SII161ACT100	ETC	获取价格	SiI 161A PanelLink Receiver
SII164	SILICONIMAGE	获取价格	Transmitter uses PanelLink Digital technology
SII164BCT64	LATTICE	获取价格	Consumer Circuit, PQFP64, MS-026ACD, TQFP-64

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