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SII2024 PDF预览

SII2024

更新时间: 2024-11-09 03:31:59
品牌 Logo 应用领域
矽映 - SILICONIMAGE 光纤
页数 文件大小 规格书
2页 999K
描述
Fibre Channel Quad SerDes

SII2024 数据手册

 浏览型号SII2024的Datasheet PDF文件第2页 
SiI 2024 Fibre Channel Quad SerDes  
Silicon Image's SiI 2024 Quad serializer/deserializer (SerDes) is capable  
of transmitting and receiving four independent channels of data at  
1.0625 and 2.125 gigabits-per-second (Gbps). Targeted at Fibre Channel  
applications, the SiI 2024 Quad SerDes is designed for power, performance  
and price. Making use of a robust CMOS design that significantly  
reduces power dissipation and jitter, the SiI 2024 provides a low-cost  
solution for applications that require multiple-channel, high-performance  
Fibre Channel SerDes. By offering four integrated, low-power SerDes in  
one package, the SiI 2024 reduces board space and power requirements  
traditionally needed for Fibre Channel SerDes.  
Fibre Channel Applications  
• Hubs and Switches  
• RAID Systems  
• High-Speed Backplanes  
On a per-channel basis, the SiI 2024 supports selectable transmit and  
receive data rates for automatic speed negotiation. It also utilizes  
10-bit SSTL_2-compatible interfaces for each channel’s parallel data  
input/output. For added flexibility in some system applications, the  
SiI 2024 offers pre-emphasis and voltage swing control on the serial  
transmit ports. The SiI 2024 is available in a 324-pin, 23x23mm PBGA  
package and supports JTAG for improved testability.  
The SiI 2024 SerDes leverages much of the circuit innovation at the  
physical layer of Silicon Image's proprietary, reduced overhead Multi-  
TM  
layer Serial Link (MSL ) architecture, pioneered and proven through  
®
TM  
the company's market-leading PanelLink and SATALink products.  
MSL technology is a multi-layer approach to providing robust, cost-  
effective, multi-gigabit semiconductor solutions on a single chip for  
high-bandwidth applications.  
Tape Backup Unit  
Fibre Channel  
Fibre Channel  
Fibre Channel  

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