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SI52143-A01AGMR PDF预览

SI52143-A01AGMR

更新时间: 2024-11-05 20:01:59
品牌 Logo 应用领域
芯科 - SILICON 时钟外围集成电路晶体
页数 文件大小 规格书
23页 397K
描述
Clock Generator, 100MHz, CMOS, 4 X 4 MM, MO-220VGGD-8, QFN-20

SI52143-A01AGMR 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HVQCCN,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.31JESD-30 代码:S-XQCC-N20
长度:4 mm端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:100 MHz封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE主时钟/晶体标称频率:25 MHz
座面最大高度:0.8 mm最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
宽度:4 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

SI52143-A01AGMR 数据手册

 浏览型号SI52143-A01AGMR的Datasheet PDF文件第2页浏览型号SI52143-A01AGMR的Datasheet PDF文件第3页浏览型号SI52143-A01AGMR的Datasheet PDF文件第4页浏览型号SI52143-A01AGMR的Datasheet PDF文件第5页浏览型号SI52143-A01AGMR的Datasheet PDF文件第6页浏览型号SI52143-A01AGMR的Datasheet PDF文件第7页 
Si52143  
PCI-EXPRESS GEN 1, GEN 2, & GEN 3 QUAD OUTPUT  
CLOCK GENERATOR WITH 25 MHZ REFERENCE CLOCK  
Features  
PCI-Express Gen 1, Gen 2, Gen 3,  
and Gen 4 common clock compliant  
Gen 3 SRNS Compliant  
Supports Serial ATA (SATA) at  
100 MHz  
Low power, push-pull HCSL  
compatible differential outputs  
No termination resistors required  
Dedicated output enable hardware  
pins for each clock output  
Spread enable pin on differential  
clocks  
Four PCI-Express clocks  
25 MHz reference clock output  
25 MHz crystal input or clock input  
Signal integrity tuning  
I2C support with readback  
capabilities  
Triangular spread spectrum profile  
for maximum electromagnetic  
interference (EMI) reduction  
Industrial temperature  
–40 to 85 °C  
3.3 V power supply  
24-pin QFN package  
Ordering Information:  
See page 18  
Applications  
Pin Assignments  
Network attached storage  
Multi-function printer  
Wireless access point  
Routers  
24  
23  
22  
21  
20  
19  
Description  
OE[3:2]1  
18  
17  
16  
15  
VDD_REF  
1
2
3
4
5
6
VDD_DIFF  
REF  
The Si52143 is a spread-spectrum enabled PCIe clock generator that can source  
four PCIe clocks and a 25 MHz reference clock. The device has three hardware  
output enable pins for enabling the outputs (on the fly while powered on), and one  
hardware pin to control spread spectrum on PCIe clock outputs. In addition to the  
hardware control pins, I2C programmability is also available to dynamically control  
skew, edge rate and amplitude on the true, compliment, or both differential signals  
on the PCIe clock outputs. This control feature enables optimal signal integrity as  
well as optimal EMI signature on the PCIe clock outputs. Refer to AN636 for  
signal integrity tuning and configurability. Measuring PCIe clock jitter is quick and  
easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at  
www.silabs.com/pcie-learningcenter.  
SSON2  
DIFF3  
DIFF3  
25  
GND  
VSS_REF  
14 DIFF2  
OE_REF1  
13  
DIFF2  
VDD_DIFF  
7
8
9
10  
11  
12  
Notes:  
1. Internal 100 kohm pull-up.  
2. Internal 100 kohm pull-down.  
Patents pending  
Functional Block Diagram  
REF  
XIN/CLKIN  
XOUT  
DIFF0  
DIFF1  
DIFF2  
PLL  
(SSC)  
Divider  
DIFF3  
SCLK  
SDATA  
Control & Memory  
OE_REF  
Control  
RAM  
OE [1:0]  
OE [3:2]  
SSON  
Rev 1.4 4/16  
Copyright © 2016 by Silicon Laboratories  
Si52143  

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