Datasheet > SI52143-A01AGMR

SI52143-A01AGMR

更新时间： 2024-11-23 20:01:59

品牌	Logo	应用领域
芯科 - SILICON		时钟外围集成电路晶体
页数	文件大小	规格书
23页	397K
描述
Clock Generator, 100MHz, CMOS, 4 X 4 MM, MO-220VGGD-8, QFN-20

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中文翻译

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技术参数
数据手册

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SI52143-A01AGMR 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	HVQCCN,	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.31	JESD-30 代码：	S-XQCC-N20
长度：	4 mm	端子数量：	20
最高工作温度：	85 °C	最低工作温度：	-40 °C
最大输出时钟频率：	100 MHz	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	主时钟/晶体标称频率：	25 MHz
座面最大高度：	0.8 mm	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	4 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, OTHER
Base Number Matches：	1

SI52143-A01AGMR 数据手册

Si52143

PCI-EXPRESS GEN 1, GEN 2, & GEN 3 QUAD OUTPUT

CLOCK GENERATOR WITH 25 MHZ REFERENCE CLOCK

Features



PCI-Express Gen 1, Gen 2, Gen 3,

and Gen 4 common clock compliant

Gen 3 SRNS Compliant

Supports Serial ATA (SATA) at

100 MHz

Low power, push-pull HCSL

compatible differential outputs

No termination resistors required

Dedicated output enable hardware

pins for each clock output

Spread enable pin on differential

clocks



Four PCI-Express clocks

25 MHz reference clock output

25 MHz crystal input or clock input

Signal integrity tuning

I²C support with readback

capabilities

Triangular spread spectrum profile

for maximum electromagnetic

interference (EMI) reduction

Industrial temperature



–40 to 85 °C

3.3 V power supply

24-pin QFN package

Ordering Information:



See page 18

Applications

Pin Assignments



Network attached storage

Multi-function printer



Wireless access point

Routers

Description

OE[3:2]¹

VDD_REF

VDD_DIFF

REF

The Si52143 is a spread-spectrum enabled PCIe clock generator that can source

four PCIe clocks and a 25 MHz reference clock. The device has three hardware

output enable pins for enabling the outputs (on the fly while powered on), and one

hardware pin to control spread spectrum on PCIe clock outputs. In addition to the

hardware control pins, I2C programmability is also available to dynamically control

skew, edge rate and amplitude on the true, compliment, or both differential signals

on the PCIe clock outputs. This control feature enables optimal signal integrity as

well as optimal EMI signature on the PCIe clock outputs. Refer to AN636 for

signal integrity tuning and configurability. Measuring PCIe clock jitter is quick and

easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at

www.silabs.com/pcie-learningcenter.

SSON²

DIFF3

GND

VSS_REF

14 DIFF2

OE_REF¹

DIFF2

VDD_DIFF

Notes:

1. Internal 100 kohm pull-up.

2. Internal 100 kohm pull-down.

Patents pending

Functional Block Diagram

REF

XIN/CLKIN

XOUT

DIFF0

DIFF1

DIFF2

PLL

(SSC)

Divider

DIFF3

SCLK

SDATA

Control & Memory

OE_REF

Control

RAM

OE [1:0]

OE [3:2]

SSON

Rev 1.4 4/16

Si52143

12 3 4 5 6 7...23

中文翻译

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与SI52143-A01AGMR相关器件

型号	品牌	获取价格	描述	数据表
SI52144	SILICON	获取价格	PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD OUTPUT GENERATOR
SI52144-A01AGM	SILICON	获取价格	PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD OUTPUT GENERATOR
SI52144-A01AGMR	SILICON	获取价格	PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD OUTPUT GENERATOR
SI52146	SILICON	获取价格	PCI-EXPRESS GEN 1, GEN 2, & GEN 3 SIX OUTPUT CLOCK GENERATOR
SI52146-A01AGM	SILICON	获取价格	Processor Specific Clock Generator, 100MHz, CMOS, MO-220, QFN-32
SI52146-A01AGMR	SILICON	获取价格	Processor Specific Clock Generator, 100MHz, CMOS, MO-220, QFN-32
SI52147	SILICON	获取价格	PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT CLOCK GENERATOR
SI52147-A01AGM	SILICON	获取价格	PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT CLOCK GENERATOR
SI52147-A01AGMR	SILICON	获取价格	PCI-EXPRESS GEN 1, GEN 2, & GEN 3 NINE OUTPUT CLOCK GENERATOR
Si52202	SILICON	获取价格	12/8/4/2-Output PCI-Express Gen 1/2/3/4 and SRIS Clock Generator

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