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SI52144-A01AGM PDF预览

SI52144-A01AGM

更新时间： 2024-11-23 09:26:03
品牌 Logo 应用领域
芯科 - SILICON 输出元件PC时钟
页数 文件大小 规格书
20页 174K
描述
PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD OUTPUT GENERATOR

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中文翻译

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SI52144-A01AGM 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：QFN包装说明：HVQCCN, LCC24,.16SQ,20
针数：24Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：1.88
系列：52144输入调节：MUX
JESD-30 代码：S-XQCC-N24长度：4 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：1
反相输出次数：2端子数量：24
实输出次数：2最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC24,.16SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
电源：3.3 V认证状态：Not Qualified
座面最大高度：0.8 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
宽度：4 mmBase Number Matches：1

SI52144-A01AGM 数据手册

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Si52144  
PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD  
OUTPUT GENERATOR  
Features  
PCI-Express Gen 1, Gen 2, &  
25 MHz crystal input or clock  
Gen 3 Compliant  
input  
2
Low power push-pull type  
I C support with readback  
differential output buffers  
capabilities  
Integrated resistors on differential  
Triangular spread spectrum  
profile for maximum  
clocks  
Dedicated output enable  
electromagnetic interference  
(EMI) reduction  
hardware pin for each clock  
Hardware selectable spread  
Industrial temperature:  
o
control  
–40 to 85 C  
Ordering Information:  
Four PCI-Express Clocks  
3.3 V power supply  
24-pin QFN package  
See page 18  
Pin Assignments  
Applications  
Network attached storage  
Multi-function printer  
Wireless access point  
Routers  
24  
23  
22  
21  
20  
19  
OE31  
VDD  
Description  
18  
17  
16  
15  
VDD  
1
2
3
4
5
6
OE11  
SSON2  
The Si52144 is a spread-controlled PCIe clock generator that can source  
four PCIe clocks simultaneously. The device has four hardware output  
enable control inputs for enabling the respective differential outputs on the  
fly while powered on along with the spread control hardware pin to enable  
DIFF3  
DIFF3  
25  
GND  
VSS  
14 DIFF2  
OE21  
VDD  
13  
DIFF2  
2
spread for EMI reduction. In addition to the hardware control pins, I C  
7
8
9
10  
11  
12  
programmability is also available to promptly achieve optimum clock  
signal integrity through skew and edge rate control on true, compliment,  
or both differential outputs as well as amplitude control.  
Notes:  
1. Internal 100 kohm pull-up.  
2. Internal 100 kohm pull-down.  
Patents pending  
Functional Block Diagram  
DIFF0  
DIFF1  
DIFF2  
DIFF3  
XIN/CLKIN  
XOUT  
PLL  
(SSC)  
Divider  
SCLK  
Control & Memory  
SDATA  
OE [3:0]  
SSON  
Control  
RAM  
Preliminary Rev. 0.1 12/11  
Copyright © 2011 by Silicon Laboratories  
Si52144  
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.  
1234567...20

中文翻译

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