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SI52146-A01AGM PDF预览

SI52146-A01AGM

更新时间: 2024-11-05 19:30:35
品牌 Logo 应用领域
芯科 - SILICON 时钟外围集成电路晶体
页数 文件大小 规格书
22页 260K
描述
Processor Specific Clock Generator, 100MHz, CMOS, MO-220, QFN-32

SI52146-A01AGM 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:HVQCCN,Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:0.7JESD-30 代码:S-XQCC-N32
JESD-609代码:e3长度:5 mm
湿度敏感等级:1端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:100 MHz封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
主时钟/晶体标称频率:25 MHz座面最大高度:0.8 mm
最大供电电压:3.465 V最小供电电压:3.135 V
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5 mm
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

SI52146-A01AGM 数据手册

 浏览型号SI52146-A01AGM的Datasheet PDF文件第2页浏览型号SI52146-A01AGM的Datasheet PDF文件第3页浏览型号SI52146-A01AGM的Datasheet PDF文件第4页浏览型号SI52146-A01AGM的Datasheet PDF文件第5页浏览型号SI52146-A01AGM的Datasheet PDF文件第6页浏览型号SI52146-A01AGM的Datasheet PDF文件第7页 
Si52146  
PCI-EXPRESS GEN 1, GEN 2, GEN 3, & GEN 4 SIX OUTPUT  
CLOCK GENERATOR  
Features  
PCI-Express Gen 1, Gen 2, Gen 3,  
and Gen 4 common clock compliant  
Gen 3 SRNS Compliant  
Supports Serial-ATA (SATA) at  
100 MHz  
Low power push-pull HCSL  
compatible differential outputs  
No termination resistors required  
Dedicated output enable pins for  
each clock  
25 MHz crystal input or clock input  
I2C support with readback  
capabilities  
Triangular spread spectrum profile  
for maximum electromagnetic  
interference (EMI) reduction  
Industrial temperature:  
–40 to 85 °C  
3.3 V Power supply  
32-pin QFN package  
Pin selectable spread control  
Up to six PCI-Express clock outputs  
Ordering Information:  
See page 18  
Applications  
Network attached storage  
Multi-function printer  
Wireless access point  
Switches  
Pin Assignments  
Description  
The Si52146 is a high-performance, PCIe clock generator that can source six  
PCIe clocks from a 25 MHz crystal or clock input. The clock outputs are  
compliant to PCIe Gen 1, Gen 2, Gen 3, Gen 3 SRNS and Gen 4 common  
clock specifications. The device has six output enable control pins for  
enabling and disabling differential outputs. A spread spectrum control pin for  
EMI reduction is also available. The small footprint and low power  
consumption makes the Si52146 the ideal clock solution for consumer and  
embedded applications. Measuring PCIe clock jitter is quick and easy with the  
Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/  
pcie-learningcenter.  
32  
31  
30  
29  
28  
27  
26  
25  
VDD_DIFF  
DIFF5  
24  
23  
VDD_DIFF  
1
2
3
4
5
6
7
8
OE_DIFF21  
SSON2  
22  
21  
DIFF5  
OE_DIFF31  
VDD_DIFF  
33  
GND  
OE_DIFF41  
OE_DIFF51  
NC  
20 DIFF4  
19  
DIFF4  
18 DIFF3  
VDD_DIFF  
17  
DIFF3  
9
10  
11  
12  
13  
14  
15  
16  
Notes:  
1. Internal 100 kohm pull-up.  
2. Internal 100 kohm pull-down.  
Functional Block Diagram  
Patents pending  
DIFF0  
XIN/CLKIN  
DIFF1  
XOUT  
PLL1  
Divider  
(SSC)  
DIFF2  
DIFF3  
DIFF4  
DIFF5  
SCLK  
Control & Memory  
SDATA  
CKPWRGD/PDB  
Control  
RAM  
OE [5:0]  
SSON  
Rev. 1.4 4/16  
Copyright © 2016 by Silicon Laboratories  
Si52146  

SI52146-A01AGM 替代型号

型号 品牌 替代类型 描述 数据表
SL28PCIe10ALCT SILICON

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