Datasheet > SDIO101IET,128

SDIO101IET,128

更新时间： 2024-11-29 20:08:19

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
38页	231K
描述
SD/SDIO/MMC/CE-ATA host controller, Package, Standard Marking, Reel Pack, SMD, 13", Turned

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SDIO101IET,128 技术参数

是否Rohs认证：	符合	生命周期：	Preview
Reach Compliance Code：	compliant	风险等级：	5.77
Base Number Matches：	1

SDIO101IET,128 数据手册

SDIO101

SD/SDIO/MMC/CE-ATA host controller

Rev. 5 — 22 August 2011

Product data sheet

1. General description

The SDIO101 is a SD/SDIO/MMC/CE-ATA host controller with a standard 16-bit

asynchronous memory interface. The device conforms to the SD Host Standard

Specification Version 2.0 (see Ref. 1). The SDIO101 manages the physical layer of SD,

SDIO, MMC and CE-ATA protocols and can be used together with SD Host Standard

compatible driver software to add SD/SDIO/MMC/CE-ATA host functionality to a variety of

microprocessor systems.

The SDIO101 supports both full-speed (< 25 MHz) and high-speed (< 52 MHz) data

transmissions on the SD/SDIO/MMC/CE-ATA port. The SDIO101 offers separate pins for

SD/SDIO/MMC/CE-ATA port supply voltage, host interface supply voltage and core supply

voltage. The SD/SDIO/MMC/CE-ATA port can operate at a wide voltage range (1.8 V to

3.6 V) which allows the device to interface to a large variety of SD, SDIO, MMC or

CE-ATA devices. The SDIO101 allows 1-bit and 4-bit SD transactions and 8-bit

MMC/CE-ATA transactions. The 16-bit asynchronous memory interface can operate at a

2.5 V to 3.6 V voltage range.

A built-in, 2 kB data buffer allows for a low interrupt latency time and efficient

communication with the host processor at high data rates. The SDIO101 provides a DMA

request line that can be connected to an external DMA controller to off-load the host

processor and increase overall system performance.

An on-board PLL allows a large range of SD/SDIO/MMC/CE-ATA clock speeds to be

generated from a single externally available clock source. An additional fractional divider

allows the SD clock speed to be fine-tuned with very fine granularity, which enables the

user to achieve the maximum desired SD clock speed from the external clock source.

The SDIO101 offers 5 levels of power saving, including a ‘Hibernate mode’ where the

on-board oscillator, PLL and data buffer memories are switched off, and a ‘Coma mode’ in

which supply power to most of the device is internally switched off. This allows the device

to be used in very power-critical applications.

2. Features and benefits

2.1 General

 Provides 1 SD/SDIO/MMC/CE-ATA slot, operating in 1-bit, 4-bit and 8-bit

(MMC/CE-ATA) modes

 2.5 V to 3.3 V host interface

 1.8 V core supply voltage

 Separate SD supply voltage pin. SD/SDIO/MMC/CE-ATA slot is able to operate at a

wide voltage range (1.8 V to 3.3 V).

12 3 4 5 6 7...38

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