Datasheet > SDIO101IHR

SDIO101IHR

更新时间： 2024-02-20 07:04:18

品牌	Logo	应用领域
恩智浦 - NXP		外围集成电路
页数	文件大小	规格书
38页	227K
描述
IC SPECIALTY MICROPROCESSOR CIRCUIT, PQCC60, 5 X 5 MM, 0.50 MM PITCH, PLASTIC, SOT1133-1, HXQFN-60, Microprocessor IC:Other

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SDIO101IHR 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	60
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
风险等级：	5.81	JESD-30 代码：	S-PQCC-N60
长度：	5 mm	湿度敏感等级：	2
端子数量：	60	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	0.5 mm
最大供电电压：	1.95 V	最小供电电压：	1.65 V
标称供电电压：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	5 mm	uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT
Base Number Matches：	1

SDIO101IHR 数据手册

SDIO101

SD/SDIO/MMC/CE-ATA host controller

Rev. 5 — 22 August 2011

Product data sheet

1. General description

The SDIO101 is a SD/SDIO/MMC/CE-ATA host controller with a standard 16-bit

asynchronous memory interface. The device conforms to the SD Host Standard

Specification Version 2.0 (see Ref. 1). The SDIO101 manages the physical layer of SD,

SDIO, MMC and CE-ATA protocols and can be used together with SD Host Standard

compatible driver software to add SD/SDIO/MMC/CE-ATA host functionality to a variety of

microprocessor systems.

The SDIO101 supports both full-speed (< 25 MHz) and high-speed (< 52 MHz) data

transmissions on the SD/SDIO/MMC/CE-ATA port. The SDIO101 offers separate pins for

SD/SDIO/MMC/CE-ATA port supply voltage, host interface supply voltage and core supply

voltage. The SD/SDIO/MMC/CE-ATA port can operate at a wide voltage range (1.8 V to

3.6 V) which allows the device to interface to a large variety of SD, SDIO, MMC or

CE-ATA devices. The SDIO101 allows 1-bit and 4-bit SD transactions and 8-bit

MMC/CE-ATA transactions. The 16-bit asynchronous memory interface can operate at a

2.5 V to 3.6 V voltage range.

A built-in, 2 kB data buffer allows for a low interrupt latency time and efficient

communication with the host processor at high data rates. The SDIO101 provides a DMA

request line that can be connected to an external DMA controller to off-load the host

processor and increase overall system performance.

An on-board PLL allows a large range of SD/SDIO/MMC/CE-ATA clock speeds to be

generated from a single externally available clock source. An additional fractional divider

allows the SD clock speed to be fine-tuned with very fine granularity, which enables the

user to achieve the maximum desired SD clock speed from the external clock source.

The SDIO101 offers 5 levels of power saving, including a ‘Hibernate mode’ where the

on-board oscillator, PLL and data buffer memories are switched off, and a ‘Coma mode’ in

which supply power to most of the device is internally switched off. This allows the device

to be used in very power-critical applications.

2. Features and benefits

2.1 General

 Provides 1 SD/SDIO/MMC/CE-ATA slot, operating in 1-bit, 4-bit and 8-bit

(MMC/CE-ATA) modes

 2.5 V to 3.3 V host interface

 1.8 V core supply voltage

 Separate SD supply voltage pin. SD/SDIO/MMC/CE-ATA slot is able to operate at a

wide voltage range (1.8 V to 3.3 V).

12 3 4 5 6 7...38

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