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SC16C852SV PDF预览

SC16C852SV

更新时间: 2024-11-02 11:56:23
品牌 Logo 应用领域
恩智浦 - NXP 先进先出芯片
页数 文件大小 规格书
48页 221K
描述
1.8 V dual UART, 20 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface

SC16C852SV 数据手册

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SC16C852SV  
1.8 V dual UART, 20 Mbit/s (max.) with 128-byte FIFOs,  
infrared (IrDA), and XScale VLIO bus interface  
Rev. 01 — 23 September 2008  
Product data sheet  
1. General description  
The SC16C852SV is a 1.8 V, low power dual channel Universal Asynchronous Receiver  
and Transmitter (UART) used for serial data communications. Its principal function is to  
convert parallel data into serial data and vice versa. The UART can handle serial data  
rates up to 20 Mbit/s (4× sampling rate). SC16C852SV can be programmed to operate in  
extended mode where additional advanced UART features are available (see  
Section 6.2). The SC16C852SV family UART provides enhanced UART functions with  
128-byte FIFOs, modem control interface and IrDA encoder/decoder. On-board status  
registers provide the user with error indications and operational status. System interrupts  
and modem control features may be tailored by software to meet specific user  
requirements. An internal loopback capability allows on-board diagnostics. Independent  
programmable baud rate generators are provided to select transmit and receive baud  
rates.  
The SC16C852SV with Intel XScale processor VLIO interface operates at 1.8 V and is  
available in the TFBGA36 package.  
2. Features  
I Dual channel high performance UART  
I 1.8 V operation  
I Advanced package: TFBGA36  
I Up to 20 Mbit/s data rate (4× sampling) at 1.8 V  
I Programmable sampling rate: 16×, 8×, 4×  
I 128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU  
I 128-byte receive FIFO with error flags to reduce the bandwidth requirement of the  
external CPU  
I 128 programmable Receive and Transmit FIFO interrupt trigger levels  
I 128 Receive and Transmit FIFO reporting levels (level counters)  
I Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) flow control  
I Programmable Xon/Xoff characters  
I 128 programmable hardware and software trigger levels  
I Automatic 9-bit mode (RS-485) address detection  
I Automatic RS-485 driver turn-around with programmable delay  
I Dual channel concurrent write  
I UART software reset  
I High resolution clock prescaler, from 0 to 15 with granularity of 116 to allow  
non-standard UART clock to be used  

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