Datasheet > SC16C852VIET,557

SC16C852VIET,557

更新时间： 2024-11-02 14:44:35

品牌	Logo	应用领域
恩智浦 - NXP		先进先出芯片
页数	文件大小	规格书
54页	235K
描述
SC16C852V - 1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared (IrDA) and XScale VLIO bus interface BGA 36-Pin

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SC16C852VIET,557 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	生命周期：	Active
零件包装代码：	BGA	包装说明：	3.50 X 3.50 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, PLASTIC, SOT-912-1, TFBGA-36
针数：	36	Reach Compliance Code：	unknown
风险等级：	5.77	Base Number Matches：	1

SC16C852VIET,557 数据手册

SC16C852V

1.8 V dual UART, 5 Mbit/s (max.) with 128-byte FIFOs, infrared

(IrDA), and XScale VLIO bus interface

Rev. 04 — 14 January 2008

Product data sheet

1. General description

The SC16C852V is a 1.8 V, low power dual channel Universal Asynchronous Receiver

and Transmitter (UART) used for serial data communications. Its principal function is to

convert parallel data into serial data and vice versa. The UART can handle serial data

rates up to 5 Mbit/s. SC16C852V can be programmed to operate in extended mode where

additional advanced UART features are available (see Section 6.2). The SC16C852V

family UART provides enhanced UART functions with 128-byte FIFOs, modem control

interface, DMA mode data transfer, and IrDA encoder/decoder. On-board status registers

provide the user with error indications and operational status. System interrupts and

modem control features may be tailored by software to meet speciﬁc user requirements.

An internal loopback capability allows on-board diagnostics. Independent programmable

baud rate generators are provided to select transmit and receive baud rates.

The SC16C852V with Intel XScale processor VLIO interface operates at 1.8 V and is

available in HVQFN48 and TFBGA36 packages.

2. Features

I Dual channel high performance UART

I 1.8 V operation

I Advanced packages: HVQFN48 and TFBGA36

I Up to 5 Mbit/s data rate at 1.8 V

I 128-byte transmit FIFO to reduce the bandwidth requirement of the external CPU

I 128-byte receive FIFO with error ﬂags to reduce the bandwidth requirement of the

external CPU

I 128 programmable Receive and Transmit FIFO interrupt trigger levels

I 128 Receive and Transmit FIFO reporting levels (level counters)

I Automatic software (Xon/Xoff) and hardware (RTS/CTS or DTR/DSR) ﬂow control

I Programmable Xon/Xoff characters

I 128 programmable hardware and software trigger levels

I Automatic 9-bit mode (RS-485) address detection

I Automatic RS-485 driver turn-around with programmable delay

I Dual channel concurrent write

I UART software reset

I High resolution clock prescaler, from 0 to 15 with granularity of ¹⁄₁₆to allow

non-standard UART clock to be used

I Industrial temperature range (−40 °C to +85 °C)

I Software compatible with industry standard SC16C652B

12 3 4 5 6 7...54

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