Datasheet > SA555DR

SA555DR

更新时间： 2024-09-17 17:14:59

品牌	Logo	应用领域
友台半导体 - UMW		/
页数	文件大小	规格书
18页	516K
描述
精密计时器

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数据手册

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SA555DR 数据手册

UMW

NA555, NE555, SA555, SE555

Features

Description

These devices are precision timing circuits capable of

producing accurate time delays or oscillation. In the

time-delay or mono-stable mode of operation, the

timed interval is controlled by a single external

resistor and capacitor network. In the a-stable mode

of operation, the frequency and duty cycle can be

controlled independently with two external resistors

and a single external capacitor.

•

Timing From Microseconds to Hours

Astable or Monostable Operation

Adjustable Duty Cycle

TTL-Compatible Output Can Sink or Source

Up to 200 mA

The threshold and trigger levels normally are two-

thirds and one-third, respectively, of V_CC. These

levels can be altered by use of the control-voltage

terminal. When the trigger input falls below the trigger

level, the flip-flop is set, and the output goes high. If

the trigger input is above the trigger level and the

threshold input is above the threshold level, the flip-

flop is reset and the output is low. The reset (RESET)

input can override all other inputs and can be used to

initiate a new timing cycle. When RESET goes low,

the flip-flop is reset, and the output goes low. When

the output is low, a low-impedance path is provided

between discharge (DISCH) and ground.

Applications

•

Fingerprint Biometrics

Iris Biometrics

•

RFID Reader

The output circuit is capable of sinking or sourcing

current up to 200 mA. Operation is specified for

supplies of 5 V to 15 V. With a 5-V supply, output

levels are compatible with TTL inputs.

Simplified Schematic

RESET

CONT

THRES

OUT

TRIG

DISCH

GND

www.umw-ic.com

友台半导体有限公司

12 3 4 5 6 7...18

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