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SA555DRG4 PDF预览

SA555DRG4

更新时间： 2024-11-18 04:06:23
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
24页 405K
描述
PRECISION TIMERS

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中文翻译

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SA555DRG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：0.62其他特性：CAN ALSO OPERATE FROM A 15V NOMINAL SUPPLY
模拟集成电路 - 其他类型：PULSE; RECTANGULARJESD-30 代码：R-PDSO-G8
JESD-609代码：e4长度：4.9 mm
湿度敏感等级：1功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：5/15 V
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：Analog Waveform Generation Functions最大供电电流 (Isup)：15 mA
最大供电电压 (Vsup)：16 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BIPOLAR温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
Base Number Matches：1

SA555DRG4 数据手册

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NA555, NE555, SA555, SE555  
PRECISION TIMERS  
www.ti.com  
SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006  
FEATURES  
•
•
Timing From Microseconds to Hours  
Astable or Monostable Operation  
•
•
Adjustable Duty Cycle  
TTL-Compatible Output Can Sink or Source  
up to 200 mA  
DESCRIPTION/ORDERING INFORMATION  
These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the  
time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and  
capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled  
independently with two external resistors and a single external capacitor.  
The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be  
altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is  
set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the  
threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs  
and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes  
low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.  
The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of  
5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.  
NA555...D OR P PACKAGE  
SE555...FK PACKAGE  
NE555...D, P, PS, OR PW PACKAGE  
(TOP VIEW)  
SA555...D OR P PACKAGE  
SE555...D, JG, OR P PACKAGE  
(TOP VIEW)  
3
2
1 20 19  
18  
1
2
3
4
GND  
TRIG  
OUT  
VCC  
8
7
6
5
NC  
NC  
TRIG  
NC  
OUT  
NC  
4
5
6
7
8
DISCH  
THRES  
CONT  
DISCH  
NC  
THRES  
NC  
17  
16  
15  
14  
RESET  
9 10 11 12 13  
NC – No internal connection  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1973–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1234567...24

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SA555DRG4 替代型号

型号 品牌 替代类型 描述 数据表
SA555DR TI

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 PRECISION TIMERS
NE555DR TI

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 PRECISION TIMERS
NE555D TI

类似代替

 PRECISION TIMERS

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