5秒后页面跳转
捷配首页

Datasheet > 信号电路 > 模拟波形发生功能> NE555DR
NE555DR PDF预览

NE555DR

更新时间： 2024-11-21 04:00:03
品牌 Logo 应用领域
德州仪器 - TI 模拟波形发生功能信号电路光电二极管PC
页数 文件大小 规格书
24页 405K
描述
PRECISION TIMERS

阅读下载

中文翻译

获取价格

NE555DR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP8,.25针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.55Samacsys Confidence：4
Samacsys Status：ReleasedSamacsys PartID：6648
Samacsys Pin Count：8Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Small Outline PackagesSamacsys Footprint Name：D (R-PDSO-G8)
Samacsys Released Date：2015-10-26 06:49:38Is Samacsys：N
其他特性：CAN ALSO OPERATE FROM A 15V NOMINAL SUPPLY模拟集成电路 - 其他类型：PULSE; RECTANGULAR
JESD-30 代码：R-PDSO-G8JESD-609代码：e3
长度：4.9 mm湿度敏感等级：1
功能数量：1端子数量：8
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP8,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：260
电源：5/15 V认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Analog Waveform Generation Functions
最大供电电流 (Isup)：15 mA最大供电电压 (Vsup)：16 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：BIPOLAR
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.9 mmBase Number Matches：1

NE555DR 数据手册

 浏览型号NE555DR的Datasheet PDF文件第2页浏览型号NE555DR的Datasheet PDF文件第3页浏览型号NE555DR的Datasheet PDF文件第4页浏览型号NE555DR的Datasheet PDF文件第5页浏览型号NE555DR的Datasheet PDF文件第6页浏览型号NE555DR的Datasheet PDF文件第7页 
NA555, NE555, SA555, SE555  
PRECISION TIMERS  
www.ti.com  
SLFS022F–SEPTEMBER 1973–REVISED JUNE 2006  
FEATURES  
•
•
Timing From Microseconds to Hours  
Astable or Monostable Operation  
•
•
Adjustable Duty Cycle  
TTL-Compatible Output Can Sink or Source  
up to 200 mA  
DESCRIPTION/ORDERING INFORMATION  
These devices are precision timing circuits capable of producing accurate time delays or oscillation. In the  
time-delay or monostable mode of operation, the timed interval is controlled by a single external resistor and  
capacitor network. In the astable mode of operation, the frequency and duty cycle can be controlled  
independently with two external resistors and a single external capacitor.  
The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be  
altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is  
set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the  
threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs  
and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes  
low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.  
The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of  
5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.  
NA555...D OR P PACKAGE  
SE555...FK PACKAGE  
NE555...D, P, PS, OR PW PACKAGE  
(TOP VIEW)  
SA555...D OR P PACKAGE  
SE555...D, JG, OR P PACKAGE  
(TOP VIEW)  
3
2
1 20 19  
18  
1
2
3
4
GND  
TRIG  
OUT  
VCC  
8
7
6
5
NC  
NC  
TRIG  
NC  
OUT  
NC  
4
5
6
7
8
DISCH  
THRES  
CONT  
DISCH  
NC  
THRES  
NC  
17  
16  
15  
14  
RESET  
9 10 11 12 13  
NC – No internal connection  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1973–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1234567...24

中文翻译

下载PDF

NE555DR 替代型号

型号 品牌 替代类型 描述 数据表
NE555DRG4 TI

完全替代

 PRECISION TIMERS
NE555DRE4 TI

完全替代

 PRECISION TIMERS
NE555DE4 TI

完全替代

 PRECISION TIMERS

与NE555DR相关器件

型号 品牌 获取价格 描述 数据表
NE555DRE4 TI

获取价格

 		PRECISION TIMERS
NE555DRG3 TI

获取价格

 		PRCISION TIMERS
NE555DRG4 TI

获取价格

 		PRECISION TIMERS
NE555DT STMICROELECTRONICS

获取价格

 		PULSE; RECTANGULAR, 0.5MHz, TIMER, PDSO8, MICRO, PLASTIC, SO-8
NE555D-T PHILIPS

获取价格

 		Analog Waveform Generation Function, BIPolar, PDSO8,
NE555F NXP

获取价格

 		Timer
NE555F-A PHILIPS

获取价格

 		Analog Waveform Generation Function, BIPolar, CDIP14
NE555F-B PHILIPS

获取价格

 		Analog Waveform Generation Function, BIPolar, CDIP14
NE555FE NXP

获取价格

 		IC SQUARE, TIMER, CDIP8, HERMETIC SEALED, CERDIP-8, Analog Waveform Generation Function
NE555FE-A PHILIPS

获取价格

 		Analog Waveform Generation Function, BIPolar, CDIP8

与NE555DR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证