Datasheet > S2042

S2042

更新时间： 2024-09-14 04:07:07

品牌	Logo	应用领域
AMCC		/
页数	文件大小	规格书
20页	230K
描述
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS

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中文翻译

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数据手册

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S2042 数据手册

PRELIMINARY

DEVICE SPECIFICATION

S2042/S2043

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS

BiCMOS PECL CLOCK GENERATOR

HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS

FEATURES

GENERAL DESCRIPTION

• Functionally compliant with ANSI X3T11 Fibre

Channel physical and transmission protocol

standards

• S2042 transmitter incorporates phase-locked loop

(PLL) providing clock synthesis from low-speed

reference

The S2042 and S2043 transmitter and receiver pair

are designed to perform high-speed serial data trans-

mission over fiber optic or coaxial cable interfaces

conforming to the requirements of the ANSI X3T11

Fibre Channel specification. The chipset is select-

able to 1062, 531 or 266 Mbit/s data rates with

associated 10- or 20-bit data word.

• S2043 receiver PLL configured for clock and

data recovery

The chipset performs parallel-to-serial and serial-to-

parallel conversion and framing for block-encoded

data. The S2042 on-chip PLL synthesizes the high-

speed clock from a low-speed reference. The S2043

on-chip PLL synchronizes directly to incoming digital

signals to receive the data stream. The transmitter

and receiver each support differential PECL-compat-

ible I/O for fiber optic component interfaces, to

minimize crosstalk and maximize data integrity. Lo-

cal loopback allows for system diagnostics. The TTL

I/O section can operate from either a +3.3V or a +5V

power supply. With a 3.3V power supply the chipset

dissipates only 1W typically.

• 1062, 531 and 266 Mb/s operation

• 10- or 20-bit parallel TTL compatible interface

• 1 watt typical power dissipation for chipset

• +3.3/+5V power supply

• Low-jitter serial PECL compatible interface

• Lock detect

• Local loopback

• 10mm x 10mm 52 PQFP package

• Fibre Channel framing performed by receiver

• Continuous downstream clocking from receiver

• TTL compatible outputs possible with +5V I/O

power supply

APPLICATIONS

Figure 1 shows a typical network configuration incor-

porating the chipset. The chipset is compatible with

AMCC’s S2036 Open Fiber Control (OFC) device.

High-speed data communications

• Supercomputer/Mainframe

• Workstation

• Switched networks

• Proprietary extended backplanes

• Mass storage devices/RAID drives

Figure 1. System Block Diagram

S2036

Open

Fiber

Control

(OFC)

Optical

S2043

S2042

Optical

Fibre

Channel

Controller

Fibre

Channel

Controller

S2042

Optical

S2043

Optical

S2036

Open

Fiber

Control

(OFC)

Applied Micro Circuits Corporation

6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333

12 3 4 5 6 7...20

中文翻译

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S20420	MICROSEMI	获取价格	Silicon Power Rectifier
S204201N1124	MICROSEMI	获取价格	SILICON POWER RECTIFIER
S204201N1124A	MICROSEMI	获取价格	SILICON POWER RECTIFIER
S204201N1125	MICROSEMI	获取价格	SILICON POWER RECTIFIER
S204201N1125A	MICROSEMI	获取价格	SILICON POWER RECTIFIER
S204201N1202	MICROSEMI	获取价格	SILICON POWER RECTIFIER
S204201N1202A	MICROSEMI	获取价格	SILICON POWER RECTIFIER
S204201N1202B	MICROSEMI	获取价格	SILICON POWER RECTIFIER
S204201N1203	MICROSEMI	获取价格	SILICON POWER RECTIFIER
S204201N1203A	MICROSEMI	获取价格	SILICON POWER RECTIFIER

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