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S2043B-05 PDF预览

S2043B-05

更新时间: 2024-09-15 19:18:23
品牌 Logo 应用领域
AMCC 电信电信集成电路
页数 文件大小 规格书
20页 229K
描述
Telecom Circuit, 1-Func, PQFP52, 10 X 10 MM, PLASTIC, QFP-52

S2043B-05 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP,针数:52
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.67JESD-30 代码:S-PQFP-G52
长度:10 mm功能数量:1
端子数量:52最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK认证状态:Not Qualified
座面最大高度:2.45 mm最大压摆率:267 mA
标称供电电压:3.3 V表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD宽度:10 mm
Base Number Matches:1

S2043B-05 数据手册

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®
PRELIMINARY  
DEVICE SPECIFICATION  
S2042/S2043  
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS  
FEATURES  
GENERAL DESCRIPTION  
• Functionally compliant with ANSI X3T11 Fibre  
Channel physical and transmission protocol  
standards  
• S2042 transmitter incorporates phase-locked loop  
(PLL) providing clock synthesis from low-speed  
reference  
The S2042 and S2043 transmitter and receiver pair  
are designed to perform high-speed serial data trans-  
mission over fiber optic or coaxial cable interfaces  
conforming to the requirements of the ANSI X3T11  
Fibre Channel specification. The chipset is select-  
able to 1062, 531 or 266 Mbit/s data rates with  
associated 10- or 20-bit data word.  
• S2043 receiver PLL configured for clock and  
data recovery  
The chipset performs parallel-to-serial and serial-to-  
parallel conversion and framing for block-encoded  
data. The S2042 on-chip PLL synthesizes the high-  
speed clock from a low-speed reference. The S2043  
on-chip PLL synchronizes directly to incoming digital  
signals to receive the data stream. The transmitter  
and receiver each support differential PECL-compat-  
ible I/O for fiber optic component interfaces, to  
minimize crosstalk and maximize data integrity. Lo-  
cal loopback allows for system diagnostics. The TTL  
I/O section can operate from either a +3.3V or a +5V  
power supply. With a 3.3V power supply the chipset  
dissipates only 1W typically.  
• 1062, 531 and 266 Mb/s operation  
• 10- or 20-bit parallel TTL compatible interface  
• 1 watt typical power dissipation for chipset  
• +3.3/+5V power supply  
• Low-jitter serial PECL compatible interface  
• Lock detect  
• Local loopback  
• 10mm x 10mm 52 PQFP package  
• Fibre Channel framing performed by receiver  
• Continuous downstream clocking from receiver  
• TTL compatible outputs possible with +5V I/O  
power supply  
APPLICATIONS  
Figure 1 shows a typical network configuration incor-  
porating the chipset. The chipset is compatible with  
AMCC’s S2036 Open Fiber Control (OFC) device.  
High-speed data communications  
• Supercomputer/Mainframe  
• Workstation  
• Switched networks  
• Proprietary extended backplanes  
• Mass storage devices/RAID drives  
Figure 1. System Block Diagram  
S2036  
Open  
Fiber  
Control  
(OFC)  
Optical  
S2043  
RX  
RX  
S2042  
TX  
Optical  
TX  
Fibre  
Channel  
Controller  
Fibre  
Channel  
Controller  
S2042  
Optical  
S2043  
RX  
Optical  
RX  
TX  
TX  
S2036  
Open  
Fiber  
Control  
(OFC)  
Applied Micro Circuits Corporation  
1
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333  

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