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RMPA0965 PDF预览

RMPA0965

更新时间: 2024-10-29 22:23:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 放大器功率放大器
页数 文件大小 规格书
6页 464K
描述
CDMA and CDMA2000-1X PowerEdge Power Amplifier Module

RMPA0965 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:SOLCC8(UNSPEC)Reach Compliance Code:compliant
风险等级:5.68特性阻抗:50 Ω
构造:COMPONENT增益:29 dB
最大输入功率 (CW):10 dBm安装特点:SURFACE MOUNT
功能数量:1端子数量:8
最大工作频率:849 MHz最小工作频率:824 MHz
最高工作温度:85 °C最低工作温度:-30 °C
封装主体材料:PLASTIC/EPOXY封装等效代码:SOLCC8(UNSPEC)
电源:3.4 V射频/微波设备类型:NARROW BAND LOW POWER
子类别:RF/Microwave Amplifiers表面贴装:YES
技术:BIPOLAR最大电压驻波比:2.5
Base Number Matches:1

RMPA0965 数据手册

 浏览型号RMPA0965的Datasheet PDF文件第2页浏览型号RMPA0965的Datasheet PDF文件第3页浏览型号RMPA0965的Datasheet PDF文件第4页浏览型号RMPA0965的Datasheet PDF文件第5页浏览型号RMPA0965的Datasheet PDF文件第6页 
September 2004  
RMPA0965  
CDMA and CDMA2000-1X PowerEdge™ Power Amplifier Module  
General Description  
Features  
The RMPA0965 power amplifier module (PAM) is designed  
for cellular band AMPS, CDMA and CDMA2000-1X  
applications. The 2 stage PAM is internally matched to 50Ω  
to minimize the use of external components and features a  
low-power mode to reduce standby current and DC power  
consumption during peak phone usage. High power-added  
efficiency and excellent linearity are achieved using our  
InGaP Heterojunction Bipolar Transistor (HBT) process.  
• Single positive-supply operation with low power and  
shutdown modes  
• 40% CDMA efficiency at +28 dBm average output power  
• 52% AMPS mode efficiency at +31 dBm output power  
• Compact LCC package ( 3.0 x 3.0 x 1.0 mm)  
• Internally matched to 50and DC blocked RF input/  
output  
• Meets CDMA2000-1XRTT performance requirements  
Device  
1
Absolute Ratings  
Symbol  
Vcc1, Vcc2  
Vref  
Parameter  
Value  
5.0  
Units  
V
Supply Voltages  
Reference Voltage  
Power Control Voltage  
RF Input Power  
2.6 to 3.5  
3.5  
V
Vmode  
Pin  
V
+10  
dBm  
°C  
T
Storage Temperature  
-55 to +150  
STG  
Note:  
1: No permanent damage with only one parameter set at extreme limit. Other parameters set to typical values.  
Functional Block Diagram  
(Top View)  
MMIC  
Vcc2  
Vcc1  
1
2
3
8
7
6
INPUT  
MATCH  
OUTPUT  
MATCH  
RF OUT  
GND  
RF IN  
Vmode  
DC BIAS CONTROL  
GND  
Vref  
4
5
(paddle ground on package bottom)  
©2004 Fairchild Semiconductor Corporation  
RMPA0965 Rev. C  

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