Datasheet > Q67100-H3261

Q67100-H3261

更新时间： 2024-09-09 22:50:35

品牌	Logo	应用领域
英飞凌 - INFINEON		存储可编程只读存储器
页数	文件大小	规格书
10页	235K
描述
Nonvolatile Memory 2-Kbit E2PROM with I2C Bus Interface with Extended Temperature Range

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中文翻译

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数据手册

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Q67100-H3261 数据手册

Nonvolatile Memory

2-Kbit E²PROM with I²C Bus Interface

with Extended Temperature Range

SDE 2526

MOS IC

Features

● Word-organized reprogrammable nonvolatile memory

in n-channel floating-gate technology (E PROM)

● 256 × 8-bit organization

● + 5 V supply voltage

● Serial 2-line bus for data input and output (I C Bus)

● Reprogramming mode, typ. 15 ms erase/write cycle

● Reprogramming by means of on-chip control

(without external control)

P-DIP-8-4

● Data retention longer than 10 years

● More than 10 reprogramming cycles per address

● Extended temperature range from – 40 to 110 °C

P-DSO-8-1

Type

Ordering Code

Q67100-H9020

Q67100-H9036

Q67100-H3261

Q67100-H3262

Package

Pin Configuration

SDE 2526-5

P-DIP-8-4

SIEMENS

SDE 2526-5 A2G

SDE 25X26 A2

SDE 25X26-5 A2G

P-DSO-8-1 (SMD)

P-DIP-8-4

SIEMENS

STANDARD

P-DSO-8-1 (SMD)

Circuit Description

I C Bus Interface

The I C Bus is a bidirectional 2-line bus for the transfer of data between various integrated circuits.

It consists of a serial data line SDA and a serial clock line SCL. The data line requires an external

pull-up resistor to V_CC(open drain output stage).

The possible operational states of the I C Bus are shown in figure 1. In the quiescent state, both

lines SDA and SCL are high, i.e. the output stage of the data line is disabled. As long a SCL remains

"1", information changes on the data bus indicate the start or the end of data transfer between two

components.

Semiconductor Group

01.96

12 3 4 5 6 7...10

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