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PYA28C256E-25CWMB PDF预览

PYA28C256E-25CWMB

更新时间: 2024-09-24 00:41:31
品牌 Logo 应用领域
PYRAMID 可编程只读存储器电动程控只读存储器电可擦编程只读存储器内存集成电路
页数 文件大小 规格书
14页 796K
描述
Access Times of 150, 200, 250 and 350ns Software Data Protection

PYA28C256E-25CWMB 技术参数

生命周期:Active包装说明:0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28
Reach Compliance Code:compliant风险等级:5.73
最长访问时间:200 ns其他特性:LG-MAX
JESD-30 代码:R-CDIP-T28长度:37.846 mm
内存密度:262144 bit内存集成电路类型:EEPROM
内存宽度:8功能数量:1
端子数量:28字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:32KX8封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
编程电压:5 V座面最大高度:5.8928 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:15.24 mm
最长写入周期时间 (tWC):10 msBase Number Matches:1

PYA28C256E-25CWMB 数据手册

 浏览型号PYA28C256E-25CWMB的Datasheet PDF文件第2页浏览型号PYA28C256E-25CWMB的Datasheet PDF文件第3页浏览型号PYA28C256E-25CWMB的Datasheet PDF文件第4页浏览型号PYA28C256E-25CWMB的Datasheet PDF文件第5页浏览型号PYA28C256E-25CWMB的Datasheet PDF文件第6页浏览型号PYA28C256E-25CWMB的Datasheet PDF文件第7页 
PYA28C256  
32K x 8 EEPROM  
FEATURES  
Access Times of 150, 200, 250 and 350ns  
Single 5V±10% Power Supply  
Software Data Protection  
CMOS & TTL Compatible Inputs and Outputs  
Endurance:  
Simple Byte and Page Write  
- 10,000 Write Cycles  
- 100,000 Write Cycles (optional)  
Low Power CMOS:  
- 60 mA Active Current  
- 300 µA Standby Current  
Data Retention: 10 Years  
Available in the following package:  
– 28-Pin 600 mil Ceramic DIP  
Fast Write Cycle Times  
– 32-Pin Ceramic LCC (450x550 mils)  
DESCRIPTIOꢀ  
The PYA28C256 is a 5 Volt 32Kx8 EEPROM. The device  
supports 64-byte page write operation. The PYA28C256  
features DATA and Toggle Bit Polling as well as a system  
software scheme used to indicate early completion of a  
Write Cycle. The device also includes user-optional soft-  
ware data protection. Data Retention is 10 Years. The  
device is available in a 28-Pin 600 mil wide Ceramic DIP  
and 32-Pin LCC.  
FUꢀCTIOꢀAL BLOCꢁ DIAꢂRAM  
PIꢀ COꢀFIꢂURATIOꢀ  
DIP (C5-1)  
LCC (L6)  
Document # EEPROM104 REV 03  
Revised July 2014  

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