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PTN3392BS/F4Y PDF预览

PTN3392BS/F4Y

更新时间: 2024-11-13 20:03:15
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
30页 237K
描述
PTN3392 - 2-lane DisplayPort to VGA adapter IC QFN 48-Pin

PTN3392BS/F4Y 技术参数

生命周期:Active零件包装代码:QFN
包装说明:7 X 7 MM, 0.85 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, MO-220, SOT619-1, HVQFN-48针数:48
Reach Compliance Code:compliant风险等级:5.56
Base Number Matches:1

PTN3392BS/F4Y 数据手册

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PTN3392  
2-lane DisplayPort to VGA adapter IC  
Rev. 4 — 8 October 2012  
Product data sheet  
1. General description  
The PTN3392 is a DisplayPort to VGA adapter IC designed to connect a DisplayPort  
source to a VGA sink. The PTN3392 integrates a DisplayPort receiver and a high-speed  
triple video digital-to-analog converter that supports display resolutions from VGA to  
WUXGA (see Table 4). The PTN3392 supports either one or two DisplayPort v1.1a lanes  
operating at either 2.7 Gbit/s or 1.62 Gbit/s per lane. The PTN3392 has ‘Flash-over-AUX’  
capability enabling simple firmware upgradability in the field.  
The PTN3392 supports I2C-bus over AUX per DisplayPort v1.1a specification (Ref. 1),  
and bridges the VESA DDC channel to the DisplayPort Interface.  
The PTN3392 is designed for single supply and minimizes application costs. It can be  
powered directly from the DisplayPort source side 3.3 V supply without a need for  
additional core voltage regulator. The VGA output is powered down when there is no valid  
DisplayPort source data being transmitted. The PTN3392 also aids in monitor detection  
by performing load sensing and reporting sink connection status to the source.  
2. Features and benefits  
2.1 VESA compliant DisplayPort v1.1a converter  
Main Link: 1-lane and 2-lane modes supported  
HBR (High Bit Rate) at 2.7 Gbit/s per lane  
RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane  
BER (Bit Error Rate) better than 109  
Down-spreading SSC (Spread Spectrum Clocking) supported  
1 MHz AUX channel  
Supports native AUX CH syntax  
Supports I2C-bus over AUX CH syntax  
Hot Plug Detect (HPD) signal to the source  
Cost-effective design optimized for VGA application  
2.2 DDC channel output  
Supports 100 kbit/s I2C-bus speed, declared in DPCD register  
Support of I2C-bus speed control by DisplayPort source via DPCD registers,  
facilitating use of longer VGA cables  
I2C Over Aux feature facilitates full support of MCCS, DDC-CI, and DDC protocols  
(see Ref. 2)  
 
 
 
 

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