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PTN3393BSY

更新时间: 2024-11-13 20:07:15
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
5页 175K
描述
PTN3393 - 2-lane DisplayPort to VGA adapter test IC QFN 40-Pin

PTN3393BSY 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:QFN包装说明:HVQFN-40
针数:40Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.57
模拟集成电路 - 其他类型:ANALOG CIRCUITJESD-30 代码:S-PQCC-N40
长度:6 mm湿度敏感等级:3
功能数量:1端子数量:40
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED座面最大高度:1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:OTHER端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6 mm
Base Number Matches:1

PTN3393BSY 数据手册

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PTN3393  
2-lane DisplayPort to VGA adapter test IC  
Rev. 2 — 27 July 2012  
Objective product brief  
1. General description  
The PTN3393 is a DisplayPort to VGA adapter IC designed to connect a DisplayPort  
source to a VGA sink. The PTN3393 integrates a DisplayPort receiver and a high-speed  
triple video digital-to-analog converter that supports display resolutions from VGA to  
WUXGA. The PTN3393 supports either one or two DisplayPort v1.1a lanes operating at  
either 2.7 Gbit/s or 1.62 Gbit/s per lane. The PTN3393 supports ‘Flash-over-AUX’  
capability enabling simple firmware upgradability in the field.  
The PTN3393 supports I2C-bus over AUX per DisplayPort v1.1a specification, and  
bridges the VESA DDC channel to the DisplayPort Interface.  
The PTN3393 is designed for single supply and minimizes application costs. It can be  
powered directly from the DisplayPort source side 3.3 V supply without a need for  
additional core voltage regulator. The VGA output is powered down when there is no valid  
DisplayPort source data being transmitted. The PTN3393 also aids in monitor detection  
by performing load sensing and reporting sink connection status to the source.  
2. Functional diagram  
PTN3393  
RX PHY  
VIDEO DAC SUBSYSTEM  
DAC  
RX PHY DIGITAL  
ISOCHRONOUS LINK  
MAIN  
TIME  
CONV.  
ANALOG  
R[7:0]  
G[7:0]  
B[7:0]  
SUBSYSTEM  
R
G
B
VGA  
DAC  
DAC  
STREAM  
DIFF CDR,  
RCV S2P  
OUTPUT  
lane 0  
lane 1  
H, V  
sync  
HSYNC  
VSYNC  
TIMING RECOVERY  
V
bias  
DIFF CDR,  
RCV S2P  
CONTROL  
FLASH MCU  
DPCD  
REGISTERS  
V
bias  
2
SCL  
SDA  
I C-BUS  
RCV  
MASTER  
MANCHESTER  
CODEC  
AUX COMMAND  
LEVEL MODULE  
AUX  
DRV  
RX ACLI  
RX DIGITAL SUBSYSTEM  
V
bias  
002aah229  
Fig 1. Functional diagram of PTN3393  

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