Datasheet > PTN36502HQ

PTN36502HQ

更新时间： 2024-03-03 10:08:57

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
58页	678K
描述
USB and DP Combo Redriver, SuperSpeed USB 3.1 Gen 1, DP V 1.2

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PTN36502HQ 数据手册

PTN36502/PTN36502A

Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver

Rev. 3 — 28 September 2018

Product data sheet

1 General description

PTN36502/PTN36502A is a Type-C USB 3.1 Gen 1/ DP1.2 combo redriver that is

optimized for USB 3.1 Gen 1 and DisplayPort applications on either the Downstream

Facing Port (DFP) or Upstream Facing Port (UFP) by following the four high-speed

differential data flows to extend the signal reach.

PTN36502/PTN36502A addresses high-speed signal quality enhancement requirements

for implementation of a USB Type-C interface in a platform that supports the VESA

DisplayPort Alt Mode Standard v1.0a, includes a DisplayPort Branch or Sink function.

PTN36502/PTN36502A has three ternary (3-level) configuration pins (SCL/C1, SDA/

C2 and EN), and depending on the state of EN pin during Power-On Reset (POR),

the device gets into GPIO mode or I²C mode. When EN is driven LOW during POR,

PTN36502/PTN36502A operates under GPIO mode, and these three ternary pins are

used to configure DFP/UFP configuration followed by mode setting (USB 3.1 Gen 1 and

DisplayPort TX and RX function selection), as well as selecting receive equalization,

transmit de-emphasis and output swing level. To support applications that require greater

level of configurability, PTN36502/PTN36502A can operate in I²C mode when EN pin is

left open (OPEN/NC) during POR.

For DisplayPort (DP) operation, PTN36502/PTN36502A has a built-in internal crossbar

function that can swap AUXP and AUXN signals for supporting plug orientation.

PTN36502/PTN36502A monitors the AUX transactions and adjusts the DisplayPort

transmitter’s output swing and emphasis setting during DP Link training accordingly.

PTN36502/PTN36502A has built-in advanced power management capability that enables

significant power saving under USB 3.1 Gen 1 Low power modes (U2/U3). It can detect

LFPS signaling and link electrical conditions and can dynamically activate/deactivate

internal circuitry and logic. The device performs these actions without host software

intervention and conserves power. The host processor keeps PTN36502/PTN36502A in

deep power saving or USB operation mode until DP Alt mode is entered.

PTN36502/PTN36502A is powered from a 1.8 V supply and it is available in an extremely

thin HX2QFN24 package with 2.4 mm x 3.2 mm x 0.35 mm and 0.4 mm pitch.

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