NXP Semiconductors
PTN36502/PTN36502A
Type-C USB 3.1 Gen 1 and DisplayPort v1.2 combo redriver
6 Pinning information
6.1 Pinning
D_IOP D_ION DRX1P DRX1N
24
23
22
21
1
2
3
4
5
6
7
8
SCL/C1
20
19
18
17
16
15
14
13
EN
SDA/C2
C_INP
C_INN
A_INP
A_INN
UAUXP
UAUXN
VDD18
DTX1N
DTX1P
DTX2P
DTX2N
DAUXP
PTN36502/
PTN36502A
GND
DAUXN
9
10
11
12
B_IOP B_ION DRX2P DRX2N
aaa-026906
Figure 2.ꢀPTN36502/PTN36502A pinning (transparent top view)
6.2 Pin description
Table 3.ꢀPin description
Symbol Pin
Type
Description
1
SCL/C1
Ternary open drain input/
output
When PTN36502/PTN36502A is operating in I2C mode, this pin is
slave I2C clock pin, and external pull-up resistor to 1.8 V or 3.3 V is
required.
When PTN36502/PTN36502A is operating in GPIO mode, this
pin has multiple functions depending on EN pin state, and is 1.8 V
tolerant. Refer to Section 7.6 for more details.
2
SDA/C2
Ternary open drain input/
output
When PTN36502/PTN36502A is operating in I2C mode, this pin is
slave I2C data pin, and external pull-up resistor to 1.8 V or 3.3 V is
required.
When PTN36502/PTN36502A is operating in GPIO mode, this
pin has multiple functions depending on EN pin state, and is 1.8 V
tolerant. Refer to Section 7.6 for more details.
3
4
C_INP
C_INN
Self-biasing differential input Differential signal from high speed RX path. C_IP makes a
differential pair with C_IN. The associated TX output pair is DTX1P
and DTX1N
5
6
A_INP
A_INN
Self-biasing differential input Differential signal from high speed RX path. A_IP makes a
differential pair with A_IN. The associated TX output pair is DTX2P
and DTX2N
7
8
UAUXP
UAUXN
I/O
Upstream AUX Channel I/O. When PTN36502/PTN36502A is
placed in DFP application, these signals should be AC coupled as
per DP spec
PTN36502_PTN36502A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 28 September 2018
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