Datasheet > PSMN2R0-30YL_10

PSMN2R0-30YL_10

更新时间： 2024-09-16 06:05:35

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
14页	236K
描述
N-channel TrenchMOS logic level FET

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PSMN2R0-30YL_10 数据手册

PSMN2R0-30YL

N-channel TrenchMOS logic level FET

Rev. 03 — 7 January 2010

Product data sheet

1. Product profile

1.1 General description

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic

package using TrenchMOS technology. This product is designed and qualified for use in

industrial and communications applications.

1.2 Features and benefits

High efficiency due to low switching

Suitable for logic level gate drive

and conduction losses

sources

1.3 Applications

Class-D amplifiers

Motor control

DC-to-DC converters

Server power supplies

1.4 Quick reference data

Table 1.

Quick reference

Symbol Parameter

Conditions

drain-source voltage T_j≥ 25 °C; T_j≤ 175 °C

Min

Typ

Max Unit

V_DS

I_D

[1]

drain current

T_mb= 25 °C; V_GS= 10 V;

see Figure 1 and 3

100

P_tot

total power

dissipation

T_mb= 25 °C; see Figure 2

Dynamic characteristics

Q_GD

gate-drain charge

V_GS= 4.5 V; I_D= 10 A;

V_DS= 12 V; see Figure 14

and 15

7.5

Q_G(tot)

total gate charge

V_GS= 4.5 V; I_D= 10 A;

V_DS= 12 V; see Figure 14

Static characteristics

R_DSon

drain-source

on-state resistance

V_GS= 10 V; I_D= 15 A;

T_j= 25 °C

1.55

mΩ

[1] Continuous current is limited by package.

12 3 4 5 6 7...14

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