Datasheet > PM73124

PM73124

更新时间： 2024-11-11 22:30:35

品牌	Logo	应用领域
PMC		/
页数	文件大小	规格书
2页	39K
描述
4 Link CES/DBCES AAL1 SAR

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中文翻译

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数据手册

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PM73124 数据手册

PM73124

AAL1gator™-4

Preliminary

4 Link CES/DBCES AAL1 SAR

(DBCES) AF-VTOA-0085. Supports

idle channel detection via processor

intervention, CAS signaling, or data

pattern detection. Provides idle

channel indication on a per channel

basis.

• Supports AAL0 mode, selectable on a

per VC basis.

• Provides transmit and receive buffers

which can be used for OAM cells as

well as any other user-generated cells

such as AAL5 cells for ATM signaling.

• Provides an optional 8/16-bit Any-

PHY™ slave interface.

• Provides a three cell FIFO for UTOPIA

loopback support on a per VC basis or

a global basis.

FEATURES

• Supports four structured/unstructured

T1 or E1 links, or one unstructured

DS3, E3 or STS-1/STM-0 link over an

AAL1 CBR ATM network.

• Compliant with ATM Forum's CES (AF-

VTOA-0078), and ITU-T I.363.1.

• Supports up to 128 VCs.

• Supports n x 64 (consecutive

channels) and m x 64 (non-

consecutive channels) structured data

format with channel associated

signaling (CAS) support.

• Internal E1/T1 clock synthesizers

provided for each line which can be

controlled via internal synchronous

residual time stamp (SRTS) or an

internal programmable weighted

moving average adaptive clocking

algorithm in unstructured mode. Clock

synthesizers can also be controlled

externally to provide customization of

SRTS or adaptive clocking methods.

• Provides transparent transmission of

CCS and CAS and termination of CAS

signaling.

TRANSMIT SECTION

• Provides individually enabled per-VC

data and signaling conditioning in the

transmit cell direction and per DS0

data and signaling conditioning in the

transmit line direction.

• Provides per-VC configuration of time

slots allocated, CAS support, partial

cell size, data and signaling

conditioning, ATM Cell header

definition.

• Generates AAL1 sequence numbers,

pointers and SRTS values in

accordance with ITU-T I.363.1.

Multicast connections are supported.

• Provides a patented frame based

calendar queue service algorithm with

anti-clumping add-queue mechanism

that produces minimal CDV. In

unstructured mode uses non-frame

based scheduling to optimize CDV.

LINE INTERFACE

• Supports the following flexible line

interfaces:

•

Four individual T1 or E1 lines.

One H-MVIP line at 8 MHz.

One unstructured DS3, E3 or STS-

1/STM-0 line.

• Provides lineside loopback support on

a per channel basis.

UTOPIA INTERFACE

• Supports 52 MHz, 8/16-bit Level 2,

Multi-Phy Mode (MPHY) with parity, 8/

16-bit Level 1, SPHY and 8-bit Level 1,

ATM Master modes.

• Compliant with ATM Forum's Dynamic

Bandwidth Circuit Emulation Service

BLOCK DIAGRAM

RSTB

SCAN_ENB

SCAN_MODEB

Line Interface

LINE_MODE

Clock

MUX

TATM_DATA[15:0]

TATM_PAR

TATM_ENB

TATM_SOC

TATM_CLAV

TATM_CLK

F0B

H-MVIP

TL_DATA[3:0]

TL_SYNC[3:0]

RPHY_ADD[4:0]

UTOPIA

Interface

TL_SIG[3:0]

RATM_DATA[15:0]

RATM_PAR

RL_DATA[3:0]

RL_SYNC[3:0]

A1SP

RATM_ENB

Direct

Mode

RL_SIG[3:0]

RATM_SOC

RATM_CLAV

RATM_CLK

TPHY_ADD[4:0]

RAM

Interface

External Clock

Interface

JTAG

Processor Interface

PMC-1991273 (P2)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

中文翻译

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PM73124?	ETC	获取价格	PMC-2000098 AAL1GATOR-4/8 Telecom Standard Product Data Sheet [1.65 MB]
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PM73141	MICROSEMI	获取价格	Telecom Circuit, 1-Func, CMOS, PBGA316, 27 X 27 MM, PLASTIC, BGA-316
PM7322?	ETC	获取价格	PMC-1940904 RCMP-800 Data Sheet [1.09 MB]
PM73-221K-RC	BOURNS	获取价格	General Purpose Inductor, 220uH, 10%, 1 Element, Ferrite-Core, SMD, ROHS COMPLIANT
PM7322-SI	PMC	获取价格	ATM Switching Circuit, 1-Func, CMOS, PQFP240, 32 X 32 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, H
PM7323	PMC	获取价格	ROUTING CONTROL, MONITORING, & POLICING 200 MBPS
PM7323?	ETC	获取价格	Data Sheet Errata\|PMC-1961118 [210 kB]?
PM7323-SI	PMC	获取价格	ROUTING CONTROL, MONITORING, & POLICING 200 MBPS
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