PM7328
S/UNI-ATLAS-1K800
Release
ATM Layer Solution
• Egress input and output interfaces
• Includes a FIFO buffered 16-bit
microprocessor bus interface for cell
insertion and extraction, deterministic
VC Table access, status monitoring
and configuration of the device.
FEATURES
support an 8 or 16 bit SCI-PHY (52 -
64 byte cell) interface using direct
addressing for up to 4 PHY devices
(Utopia Level 1) and Multi-PHY
addressing for up to 32 PHY devices
(Utopia Level 2).
• Monolithic single chip device which
handles bi-directional ATM Layer
functions including VPI/VCI address
translation, cell appending, policing
(ingress only), cell counting and OAM
requirements for 1024 VCs (virtual
connections).
• Supports DMA access for cell
extraction.
• Compatible with the PM7329 S/UNI-
APEX-1K800 Traffic Manager, and
PMC-Sierra’s VORTEX Architecture.
• The UTOPIA and external SRAM
interfaces are 52 MHz max.
• Instantaneous bi-directional transfer
rate of 800 Mbit/s supports a bi-
directional cell transfer rate of
1.42x106 cell/s.
POLICING
• Ingress functionality includes a highly
flexible search engine that covers the
entire PHYID/VPI/VCI address range,
dual leaky bucket policing, per-VC cell
counts, OAM-FM and OAM-PM
processing.
• ITU-I.371, ATM Forum TM4.0
compliant, per-VC programmable dual
leaky bucket policing with a
programmable action (tag, discard, or
count only) for each bucket, each with
3 programmable 16 bit non-compliant
cell counts.
• Ingress input interface supports an 8 or
16 bit PHY interface using direct
addressing for up to 4 PHY devices
(Utopia Level 1) and Multi-PHY
addressing for up to 32 PHY devices
(Utopia Level 2).
• Egress functionality includes direct
address lookup, per-VC cell counts,
OAM-FM and OAM-PM processing.
Per-PHY output buffering scheme
resolves the head-of-line blocking
issue.
• Per-PHY single leaky bucket policing
with a programmable action (tag,
discard, or count only).
• Ingress output interface supports an 8
or 16 bit SCI-PHY (52 - 64 byte cell)
interface (Utopia Level 1) to a switch
fabric.
To External Synchronous SRAM
BLOCK DIAGRAM
SCI-PHY Level 1/ Level 2
Interface (Master)
SCI-PHY Level 1
Interface (Slave)
ODAT[15:0]
OPRTY
OSOC
OFCLK
OCA
RDAT[15:0]
RPRTY
RDRENB[1]
Ingress
Search
Engine
Ingress
Cell
Processor
Ingress
Output Cell
Interface
RCA[1]
RADDR[4:3]/RCA[3:2]
RAVALID/RCA[4]
RADDR[2:0]/RRDENB[4:2]
RSOC
Ingress
Input Cell
Interface
ORDENB
OTSEN
Ingress
Backward
Cell
Egress
Backward
Cell
RFCLK
RPOLL
PHY
Statistics
Collection
Interface
Interface
IDAT[15:0]
IPRTY
IFCLK
ISOC
ICA[1]
IWRENB[1]
IAVALID/ICA[4]
IADDR[4:3]/ICA[3:2]
IADDR[2:0]/IWRENB[4:2]
IPOLL
TDAT[15:0]
TPRTY
TWRENB[1]
Egress
Input Cell
Interface
Egress
Output Cell
Egress
Cell
Processor
TCA[1]
TADDR[4:3]/TCA[3:2]
TAVALID/TCA[4]
TADDR[2:0]/TDWRENB[4:2]
TSOC
Ingress
Microprocessor Cell
Interface
Egress
Microprocessor Cell
Interface
TFCLK
TPOLL
JTAG
Interface
Microprocessor Interface
SCI-PHY Level 1/ Level
2 Interface (Master)
SCI-PHY Level 1/ Level
2 Interface (Slave)
To External Synchronous SRAM
PMC-2010037 (r2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2001