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PM7326

更新时间: 2024-09-23 22:44:23
品牌 Logo 应用领域
PMC 开关异步传输模式ATM
页数 文件大小 规格书
2页 35K
描述
ATM/PACKET Traffic Manager and Switch

PM7326 数据手册

 浏览型号PM7326的Datasheet PDF文件第2页 
PM7326  
PMC-Sierra,Inc.  
S/UNI-APEX  
ATM/PACKET Traffic Manager and Switch  
Traffic queuing algorithm is highly  
configurable on a per connection, per  
class, and per port basis.  
Configurable scheduling of 4 classes  
of service on every port, with rate  
shaping available for the 4 WAN ports.  
Configurable traffic parameters  
enabling a mix of CBR, VBR, GFR,  
and UBR classes.  
Configurable OAM cell queuing and  
special handling on all ports.  
VPI/VCI header mapping.  
Or single port slave.  
FEATURES  
• ATM (fixed length cell) and packet/  
frame traffic manager and switch.  
• 2048 line ports, 4 WAN ports, and a  
high speed microprocessor port. Any  
port to any port switching for 64k  
independent connections.  
• Manages up to 256k cell (16M byte)  
MICROPROCESSOR INTERFACE  
66 MHz, 32 bit address/data bus  
capable of single or burst access to  
internal registers and cell buffers.  
Supports cell/packet transfer to/from  
any port, with CRC32 and CRC10  
calculation supported in hardware.  
Works seamlessly with  
S/UNI-VORTEX and S/UNI-DUPLEX  
to implement a system-wide  
embedded communication channel.  
data buffer and 4M byte context  
memory shared over all ports.  
• Configurable progressive throttling of  
buffer consumption, with memory  
Supports 700 Mb/s ingress traffic and  
reservation under high consumption.  
700 Mb/s egress traffic aggregated  
Supports ABR with EFCI marking.  
across all ports.  
CONGESTION CONTROL  
Traffic discard thresholds configurable  
per connection (independent CLP0  
and CLP1 thresholds), per class, per  
port, and per direction.  
• Buffer congestion controlled via Partial  
Low power 3.3/2.5V CMOS.  
Packet Discard, Early Packet Discard  
Standard 5 pin P1149 JTAG port.  
(PPD/EPD). Cell at a time discard also  
352 ball SBGA, 35mm x 35mm.  
supported.  
Guaranteed Frame Rate (GFR)  
implemented via CLP0 minimum buffer  
size reservation per connection.  
• For frame/packet flows:  
BUS INTERFACES  
8/16 bit, 52 MHz UTOPIA L2 bus.  
Line side:  
Supports external wire speed HDLC  
processor, SAR, and flow classifier  
via packet-contiguous queuing and  
scheduling.  
QUEUING & SCHEDULING  
Enhanced UTOPIA Tx master  
supports 2048 ports. Rx master  
supports 32 ports.  
64k traffic staging queues (one per  
connection) individually assignable to  
any CoS on any port.  
8k + 20 scheduling queues: 4 CoS  
queues per port, 2048 line ports, 4  
WAN ports, and 1 processor port.  
Error indication in AAL5 EOM trailer  
(set by SAR or classifier) can invoke  
errored packet discard, thereby  
eliminating need for packet buffers  
in external devices.  
Or single port slave.  
WAN side:  
Master (with optional cell length  
expansion) supports 4 Tx or Rx  
ports.  
BLOCK DIAGRAM  
Processor  
Interface  
Ctrl Lines  
AD[31:0]  
SSRAM Interface  
LRCLK  
LRPA  
LRSX  
LTCLK  
LTPA  
LTSX  
LRSOP  
Loop Rx  
Loop Tx  
LTSOP  
LRDAT[15:0]  
LRPRTY  
LRENB  
Any-PHY  
Que Management &  
Scheduling  
Any-PHY  
LTDAT[15:0]  
LTPRTY  
LTENB  
LRADR[5:0]  
LTADR[11:0]  
WRCLK  
WRPA  
WTCLK  
WTPA  
WRSX  
WTSX  
WRSOP  
WAN Rx  
Any-PHY  
WAN Tx  
Any-PHY  
WTSOP  
WRDAT[15:0]  
WRPRTY  
WRENB  
WTDAT[15:0]  
WTPRTY  
WTENB  
JTAG Test  
Access Port  
SDRAM Interface  
WRADR[2:0]  
WTADR[2:0]  
PMC-990146 (P2)  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERSINTERNAL USE  
© 1999 PMC-Sierra, Inc.  

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