Datasheet > PLL2014X

PLL2014X

更新时间： 2024-09-20 23:28:43

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描述
PLL2014X 20MHZ~170MHZ FSPLL\|Data Sheet

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数据手册

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PLL2014X 数据手册

20MHz ~ 170MHz FSPLL

PLL2014X

DEC 98 Version1.0

General Description

Features

The PLL2014X is a Phase-Locked Loop (PLL)

frequency synthesizer constructed in CMOS on

single monolithic structure.

¡ ß

0.25um CMOS device technology

1.8 Volt Single power supply

Output frequency range: 20~ 170 MHz

Jitter ±150ps

The PLL macrofunctions provide frequency

multiplication capabilities.

The output clock frequency Fout is related

to the reference input clock frequency

Fin by the following equation:

Duty ratio 40% to 60% at 170MHz

Frequency changedby programmable divider

Power down mode

Fout = ( m*Fin ) / ( p* 2^S)

Where,

Fout is the output clock frequency.

Fin is the reference input clock frequency.

m,p and s are the values for programmable dividers.

PLL2014X consists of a phase/Frequency Detector(PFD),

a Charge Pump an External Loop Filter, a Voltage

Controlled Oscillator(VCO), a 6bit Pre-divider,

an 8bit Main divider and 2bit Post Scaler

as shown in Figure1.

FUNCTIONAL BLOCK DIAGRAM

Fin

Charge

Pump

Pre Divider

Loop

Filter

(External)

Fout

PFD

VCO

Post Scaler

Main Divider

Figure 1. Phase Lockd Loop Block Diagram

SAMSUNG ELECTRONICS Co. LTD

12 3 4 5 6 7...12

中文翻译

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