Datasheet > PLL2027XA

PLL2027XA

更新时间： 2024-09-20 23:28:43

品牌	Logo	应用领域
其他 - ETC		时钟发生器
页数	文件大小	规格书
11页	122K
描述
PLL2027XA 20MHZ~200MHZ PIXEL CLOCK GENERATOR\|Data Sheet

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PLL2027XA 数据手册

20MHz ~ 200MHz PIXEL CLOCK GENERATOR

PLL2027XA

General Description

Features

• 0.35um CMOS device technology

• 3.3 Volt single power supply

• Input Frequency Range: 15K ~ 250KHz

• Output frequency range: 20M ~ 200MHz

• Clock-to-Clock Jitter ±150ps at 200MHz

• Duty ratio 45% to 55%(All tuned range)

• Frequency changed by programmable

divider

The PLL2027XA is a Phase-Locked Loop (PLL) frequency

synthesizer constructed in CMOS on single monolithic

structure. The PLL macrofunctions provide frequency

multiplication capabilities.

The output clock frequency Fout is related to the reference

input clock frequency Fin by the following equation:

Fout=((M+2)*Fin)/(2^P*2^S)

• Power down mode

Where, Fout is the output clock frequency.

Fin is the reference input clock frequency.

m,p and s are the values for programmable dividers.

PLL2027XA consists of a phase/Frequency Detector(PFD),

a Charge Pump an External Loop Filter, a Voltage

Controlled Oscillator(VCO), a 2bit Pre-divider, an 14bit

Main divider and 2bit Post Scaler as shown in Figure1.

FUNCTIONAL BLOCK DIAGRAM

FOUT

FIN

Pre Divider

PFD

Charge

Pump

VCO

Post Scaler

Loop

Filter

Main Divider

Figure 1. Phase Locked Loop Block Diagram

Ver 2.1 (AUG. 2000 )

No responsibility is assumed by SEC for its use nor for

any infringements of patents or other rights of third parties

that may result from its use. The contents of the datasheet

is subject to change without any notice.

SAMSUNG ELECTRONICS Co. LTD

12 3 4 5 6 7...11

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