50MHz ~ 300MHz FSPLL
PLL2108X
Ver 1.3.0. (May. 2002)
GENERAL DESCRIPTION
FEATURES
0.13um CMOS device technology
•
The pll2108x is
a
Phase Locked Loop (PLL)
frequency synthesizer. The PLL provides frequency
multiplication capabilities. The output clock frequency
FOUT is related to the input clock frequency FIN by
the following equation:
• 1.2 Volt single power supply
• Output frequency range: 50M ~ 300MHz
• Jitter: ±150ps at 300MHz
FOUT=(m*FIN) / (p*2s)
• Duty ratio: 40% to 60% (All tuned range)
• Power down mode
Where FOUT is the output clock frequency. FIN is
the input clock frequency. m, p and s are the values
for programmable dividers. pll2108x consists of
a
• Off-chip loop filter
Phase Frequency Detector(PFD), a Charge Pump, an
Off-chip Loop Filter, a Voltage Controlled Oscillator
(VCO), a 6bit Pre-divider, an 8bit Main-divider and
2bit Post-scaler as shown in functional block diagram.
• Frequency is changed by programmable divider
NOTE
1. Don't set the P or M value as zero, that is, seting the P=000000, M=00000000 can cause malfunction of the PLL.
2. The proper range of P and M : 1<=P<=62, 1<=M<=248
3. The P and M must be selected considering stability of PLL and VCO output frequency range.
4. Please contact SEC application engineer for proper selection of the P, M, S values of the PLL.
No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that
may result from its use. The contents of the datasheet is subject to change without any notice.
FUNCTIONAL BLOCK DIAGRAM
FILTER
AVDD12D AVSS12D
Fin/P
UP
DN
R1
C2
Phase
Frequency
Detector
FIN
Charge
Pump
Pre-Divider
(P)
Fvco/M
6b
Voltage
Controlled
Oscillator
M[7:0]
P[5:0]
S[1:0]
Fvco
Vctrl
Main-Divider
(M)
8b
Post - Scaler
(S)
FOUT
PWRDN
(1,2,4,8)
AVDD12A AVSS12A
VABB
2b
SAMSUNG ELECTRONICS Co. LTD