Datasheet > PLL2126X

PLL2126X

更新时间： 2024-11-09 23:28:43

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描述
PLL2126X 20MHz ~ 100MHz FSPLL\|Data Sheet

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数据手册

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PLL2126X 数据手册

20MHz ~ 100MHz FSPLL

PLL2126X

Ver 0.0

GENERAL DESCRIPTION

FEATURES

0.13um CMOS device technology

•

The pll2126x is

Phase Locked Loop (PLL)

frequency synthesizer. The PLL provide frequency

multiplication capabilities. The output clock frequency

FOUT is related to the input clock frequency FIN by

the following equation:

• 1.2 Volt single power supply

• Output frequency range: 20M ~ 100MHz

• Jitter: ±200ps at 100MHz

FOUT=(m*FIN) / (p*2^s)

• Duty ratio: 40% to 60% (All tuned range)

• Power down mode

Where FOUT is the output clock frequency. FIN is

the input clock frequency. m, p and s are the values

for programmable dividers. pll2126x consists of

• Off-chip loop filter

Phase Frequency Detector(PFD), a Charge Pump, an

Off-chip Loop Filter, a Voltage Controlled Oscillator

(VCO), a 6bit Pre-divider, an 8bit Main-divider and

2bit Post-scaler as shown in functional block diagram.

• Frequency is changed by programmable divider

NOTE

1. Don't set the P or M as zero, that is 000000 / 00000000

2. The proper range of P and M : 1<=P<=62, 1<=M<=248

3. The P and M must be selected considering stability of PLL and VCO output frequency range

4. Please consult with SEC application engineer to select the proper P, M and S values

No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that

may result from its use. The contents of the datasheet is subject to change without any notice.

FUNCTIONAL BLOCK DIAGRAM

FILTER

AVDD12D AVSS12D

Fin/P

Phase

Frequency

Detector

FIN

Charge

Pump

Pre-Divider

(P)

Fvco/M

Voltage

Controlled

Oscillator

M[7:0]

P[5:0]

S[1:0]

Fvco

Vctrl

Main-Divider

(M)

Post - Scaler

(S)

FOUT

PWRDN

(1,2,4,8)

AVDD12A AVSS12A

VABB

SAMSUNG ELECTRONICS Co. LTD

12 3 4 5 6 7...11

中文翻译

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